News Column

"Offset Integrated Circuit Packaging Interconnects" in Patent Application Approval Process

June 12, 2014



By a News Reporter-Staff News Editor at Politics & Government Week -- A patent application by the inventors Zhang, Leilei (Sunnyvale, CA); Bokharey, Zuhair (Fremont, CA), filed on November 21, 2012, was made available online on May 29, 2014, according to news reporting originating from Washington, D.C., by VerticalNews correspondents.

This patent application is assigned to Nvidia Corporation.

The following quote was obtained by the news editors from the background information supplied by the inventors: "Embodiments of the present invention generally relates to integrated circuit packaging interconnects.

"Integrated circuit (IC) fabrication is a multi-step sequence which includes processes such as patterning, deposition, etching, and metallization. Typically, in the final processing steps, the resulting IC die are separated and packaged. IC packaging serves several purposes, including providing an electrical interface with the die, providing a thermal medium through which heat may be removed from the die, and/or providing mechanical protection for the die during subsequent usage and handling.

"One type of IC packaging technique is referred to as 'flip chip' packaging. In flip chip packaging, after the metallization process is complete, solder bump structures (e.g., solder balls, pads, etc.) are deposited on the die, and the die is separated from the wafer (e.g., via dicing, cutting, etc.). The die is then inverted and positioned on a substrate so that the solder bumps align with electrical connections formed on the substrate. Heat is applied via a solder reflow process to re-melt the solder bumps and attach the die to the substrate. The die/substrate assembly may further be underfilled with a non-conductive adhesive to strengthen the mechanical connection between the die and the substrate.

"IC fabrication techniques have enabled the production of larger-sized die having higher and higher transistor densities. Consequently, IC packaging techniques have encountered challenges for providing packaging which supports the requisite number of electrical connections. In general, as the size of the die and number of electrical connections to the die is increased, the size of the package is increased. Further, as package size is increased, the thermal properties of the die and packaging materials become a more important factor.

"One relevant thermal property of the die and packaging materials is the coefficient of thermal expansion (CTE). In flip chip packaging, for example, during the solder reflow process, the die is attached to the substrate at an elevated temperature. Upon cooling, a CTE mismatch between the die and the substrate may cause shear and/or tensile stresses on the solder bump structures which attach the die to the substrate. Consequently, repeatedly cycling the IC package from an operating temperature to a non-operating temperature may result in failure of the solder bump structures.

"Accordingly, there is a need in the art for a more effective way of reducing the incidence of solder bump structure failure caused by thermal cycling of an IC package."

In addition to the background information obtained for this patent application, VerticalNews journalists also obtained the inventors' summary information for this patent application: "One embodiment of the present invention sets forth an integrated circuit package including a substrate, an integrated circuit die, and a plurality of solder bump structures. The substrate has a first coefficient of thermal expansion and includes a first plurality of interconnects disposed on a first surface of the substrate. The integrated circuit die has a second coefficient of thermal expansion and includes a second plurality of interconnects disposed on a first surface of the integrated circuit die. The plurality of solder bump structures couple the first plurality of interconnects to the second plurality of interconnects. The first plurality of interconnects are configured to be substantially aligned with the second plurality of interconnects when the integrated circuit package is at a first temperature within a range of about 0.degree. C. to about -100.degree. C. The first plurality of interconnects are configured to be offset from the second plurality of interconnects when the integrated circuit package is at a temperature above the first temperature.

"Further embodiments provide a method for fabricating an integrated circuit package.

"One advantage of the disclosed technique is that, by shifting the incidence of tensile and shear stresses from low temperatures, when the solder bump structures are cold and brittle, to high temperatures, when the solder bump structures are warm and ductile, the likelihood of failure of the solder bump structures is reduced.

BRIEF DESCRIPTION OF THE DRAWINGS

"So that the manner in which the above recited features of the invention can be understood in detail, a more particular description of the invention, briefly summarized above, may be had by reference to embodiments, some of which are illustrated in the appended drawings. It is to be noted, however, that the appended drawings illustrate only typical embodiments of this invention and are therefore not to be considered limiting of its scope, for the invention may admit to other equally effective embodiments.

"FIGS. 1A and 1B illustrate schematic views of an integrated circuit package having a conventional configuration;

"FIGS. 2A-2C illustrate an offset integrated circuit package having aspects of an embodiment of the present invention;

"FIGS. 3A and 3B illustrate the offset integrated circuit package of FIGS. 2A and 2B after solder reflow processing; and

"FIG. 4 is a flow diagram illustrating a method for fabricating an integrated circuit package according to an embodiment of the present invention."

URL and more information on this patent application, see: Zhang, Leilei; Bokharey, Zuhair. Offset Integrated Circuit Packaging Interconnects. Filed November 21, 2012 and posted May 29, 2014. Patent URL: http://appft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&u=%2Fnetahtml%2FPTO%2Fsearch-adv.html&r=5100&p=102&f=G&l=50&d=PG01&S1=20140522.PD.&OS=PD/20140522&RS=PD/20140522

Keywords for this news article include: Nvidia Corporation.

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Source: Politics & Government Week


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