This patent application is assigned to Hgst Netherlands B.v.
The following quote was obtained by the news editors from the background information supplied by the inventors: "Many data communication systems use error correction encoders and decoders to detect and correct errors in data. A data communication system may, for example, correct random errors that are generated at a rate of about 1.times.10.sup.-4. To protect against an error rate of about 1.times.10.sup.-4, an error correction encoder generates encoded bits having about 10% more bits than its input bits.
"Phase change memory (PCM) is a class of non-volatile memory. PCM devices have many advantages over traditional non-volatile flash memory. However, PCM devices may generate a large number of errors that are induced by degradation. For example, a PCM device may generate errors at a rate of 1.times.10.sup.-2 or greater.
"At the limits of endurance, the error rate in non-volatile memory devices is dominated by degradation. Errors that are caused by degradation include stuck-at faults, which have different statistics and properties than the random errors that are common in data communication systems."
In addition to the background information obtained for this patent application, VerticalNews journalists also obtained the inventors' summary information for this patent application: "According to some embodiments, a data storage system includes a memory circuit comprising memory cells and a control circuit. The control circuit generates a first set of redundant bits indicating bit positions of the memory cells having stuck-at faults in response to a first write operation if a first rate of the stuck-at faults in the memory cells is greater than a first threshold. First data bits are stored in the memory cells during the first write operation. The control circuit is operable to encode second data bits to generate first encoded data bits and a second set of redundant bits that indicate a transformation performed on the second data bits to generate the first encoded data bits in response to a second write operation if a second rate of stuck-at faults in the memory cells is greater than a second threshold. The first encoded data bits are stored in the memory cells during the second write operation. The first encoded data bits stored in the memory cells having the stuck-at faults match digital values of corresponding ones of the stuck-at faults.
"Various objects, features, and advantages of the present invention will become apparent upon consideration of the following detailed description and the accompanying drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
"FIG. 1 illustrates an example of a data storage system, according to an embodiment of the present invention.
"FIG. 2 is a flow chart that illustrates examples of operations for selecting an encoding technique to apply to data bits provided for storage in memory cells of a memory circuit, according to an embodiment of the present invention.
"FIG. 3 illustrates examples of operations that may be performed to determine the bit error rate of stuck-at faults in the memory cells, according to an embodiment of the present invention."
URL and more information on this patent application, see: Guyot, Cyril; Franca-Neto, Luiz; Mateescu, Robert Eugeniu; Bandic, Zvonimir; Wang, Qingbo. Techniques for Storing Bits in Memory Cells Having Stuck-At Faults. Filed
Keywords for this news article include: Hgst Netherlands B.v., Information Technology, Information and
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