News Column

Researchers Submit Patent Application, "Nonvolatile Memory Apparatus, Operating Method Thereof, and Data Processing System Having the Same", for...

July 1, 2014



Researchers Submit Patent Application, "Nonvolatile Memory Apparatus, Operating Method Thereof, and Data Processing System Having the Same", for Approval

By a News Reporter-Staff News Editor at Information Technology Newsweekly -- From Washington, D.C., VerticalNews journalists report that a patent application by the inventors LEE, In Soo (Icheon-si, KR); BAE, Ji Hyae (Icheon-si, KR), filed on March 18, 2013, was made available online on June 19, 2014.

The patent's assignee is Sk Hynix Inc.

News editors obtained the following quote from the background information supplied by the inventors: "The present invention generally relates to a semiconductor apparatus, and more particularly, to a nonvolatile memory apparatus, an operating method thereof, and a data processing system having is the same.

"A nonvolatile memory apparatus may include a flash memory, a phase change RAM (PCRAM), a resistive RAM (ReRAM), a magnetic RAM (MRAM) and the like. In particular, the PCRAM or MRAM is a nonvolatile memory apparatus which writes and senses data according to a current driving method.

"During a program operation for a nonvolatile memory cell, a program and verify (PNV) operation is performed to accurately write data.

"Particularly, in the nonvolatile memory apparatus based on the current driving method, a resistance distribution of each cell may deviate from a desired range after a program operation, due to various factors existing on a program path and a non-uniform resistance distribution of each cell. When the resistance distribution deviates from the desired range, a sensing margin may be degraded. In this case, it is impossible to guarantee the reliability of read data. Therefore, the program operation of the nonvolatile memory apparatus accompanies a verify process through which the resistance distribution of each cell is adjusted within the desired range.

"In general, a PNV (program and verify) pulse (a) is enabled during one period of a data write operation, and a program pulse (b) is enabled to write data into a cell during a part of the PNV period. Furthermore, after the program pulse (b) is disabled, a verify and compare pulse is enabled to check whether accurate data was written into the cell or not, thereby determining whether an additional program operation is required or not.

"The nonvolatile memory apparatus has developed from a single-level cell (SLC) method to a multi-level cell (MLC) method. Regardless of whether the nonvolatile memory apparatus is implemented based on the SLC method or the MLC method, a PNV process for each data level is performed according to a predetermined timing.

"Referring to FIG. 2, (a) represents a pulse which is enabled while all data are programmed into a memory cell array (t101 to t108), for example, a write enable pulse WE. Here, t101 to t108 may be timing periods. Further, (b1), (b2), and (b3) represent PNV pulses when data having a relatively long program time (for example, first data) are written, and (c1), (c2), and (c3) represent PNV pulses when data having a relatively short program time (for example, second data) are written.

"Referring to (b1) and (c1), PNV pulses for writing first and second data is enabled at the same time as the pulse (a) is enabled at the time point t101. In this case, since a PNV time for the second data is relatively short, the PNV pulse for the second data is disabled at the time point t102, but the PNV pulse for the first data is disabled at the time point t103.

"Therefore, during a time .DELTA.t1 required until the PNV pulse for the first data is disabled after the PNV pulse for the second data is disabled, devices to perform a program operation for the second data is are in a waiting state.

"Referring to (b2) and (c2), a PNV pulse for the first data is enabled to perform a PNV operation at the time point t101. At this time, a PNV pulse for the second data is disabled. After the PNV pulse for the first data is disabled at the time point t103, the PNV pulse for the second data is enabled to perform a PNV operation for the second data from the time point t104 to the time point t105. Then, the PNV pulse for the first data is enabled again at the time point t106.

"In this case, while the PNV operation for the first data is performed (.DELTA.t2), devices to perform the PNV operation for the second data are in a waiting state, and while the PNV operation for the second data is performed (.DELTA.t3), devices to perform the PNV operation for the first data are in a waiting state.

"Referring to (b3) and (c3), after a PNV operation for the first data is completed (t101.about.t107), a PNV operation for the second data is performed (t107.about.t108). Therefore, during a time .DELTA.t4, the devices to perform the PNV operation for the second data are in a waiting state, and during a time .DELTA.t5, the devices to perform the PNV operation for the first data are in a waiting state.

"In this PNV method, after the program operations for all data are completed, the verify operations are performed at a time or the data are reprogrammed (b1 and c1). The PNV operation is alternately performed for the respective data levels (b2 and c2). Alternatively, after a PNV operation for any one data level is completed, a PNV operation for another data level is performed (b3 and c3).

"Therefore, when data having a short program time is programmed and verified, the next PNV operation is performed after a program operation for data having a long program time is ended. Therefore, a long time is required for the program operation. In order to accurately write data, the number of PNV operations is inevitably increased. As the number of PNV operations is increased, the waiting time is accumulated to increase the entire PNV time. Accordingly, the performance of the entire system may be degraded."

As a supplement to the background information on this patent application, VerticalNews correspondents also obtained the inventors' summary information for this patent application: "In one embodiment of the present invention, there is provided a nonvolatile memory apparatus which writes data into a memory cell according to a PNV method, wherein the nonvolatile memory apparatus performs a PNV operation for first data during a first time, and performs a plurality of PNV operations for second data during the first time.

"In an embodiment of the present invention, a nonvolatile memory apparatus includes: a memory cell array including a plurality of memory cells connected between a plurality of word lines and bit lines; a decoder configured to select a word line and a bit line which are connected to a memory cell to be selected; a write driver/sense amplifier (WD/SA) circuit configured to write data into a selected memory cell and read data from a selected memory cell; a is determination unit configured to determine whether or not to repeat a PNV operation for each level of data to be programmed during a program mode, and generate a flag signal; and a controller configured to control the decoder and the WD/SA circuit to selectively access a memory cell for each level of the data, in response to the flag signal.

"In an embodiment of the present invention, an operating method of a nonvolatile memory apparatus includes the steps of: entering a program mode, as an address, data, and a program command are transmitted from a host; performing a PNV operation for first data to be programmed during a first time; and performing a plurality of PNV operations for second data to be programmed during the first time.

"In an embodiment of the present invention, a data processing system includes: a nonvolatile memory apparatus; and a memory controller configured to access the nonvolatile memory apparatus in response to a request of a host, wherein the nonvolatile memory apparatus writes data into a memory cell according to a PNV method, performs a PNV operation for first data during a first time, and performs a plurality of PNV operations for second data during the first time.

"In an embodiment of the present invention, a data processing system includes: a processor configured to control overall operations; a working memory configured to store applications, data, and control signals, which are required for operating the processor; a is nonvolatile memory apparatus accessed by the processor; and a user interface configured to perform a data I/O between the processor and a user, wherein the nonvolatile memory apparatus writes data into a memory cell according to a PNV method, performs a PNV operation for first data during a first time, and performs a plurality of PNV operations for second data during the first time.

BRIEF DESCRIPTION OF THE DRAWINGS

"Features, aspects, and embodiments are described in conjunction with the attached drawings, in which:

"FIG. 1 is a timing diagram for explaining a general PNV pulse;

"FIG. 2 is a timing diagram for explaining a general PNV process;

"FIG. 3 is a timing diagram for explaining a PNV process according to one embodiment of the present invention;

"FIG. 4 is a block diagram of a nonvolatile memory apparatus according to the embodiment of the present invention;

"FIG. 5 is a block diagram of a determination unit of FIG. 4;

"FIG. 6 is a block diagram of a PNV control unit of FIG. 4;

"FIG. 7 is a flowchart for explaining an operating method of the nonvolatile memory apparatus according to the embodiment of the present invention;

"FIG. 8 is a timing diagram for explaining a PNV process based on flag generation according to the embodiment of the present is invention;

"FIG. 9 is a block diagram of a data processing system according to the embodiment of the present invention; and

"FIG. 10 is a block diagram of a data processing system according to another embodiment of the present invention."

For additional information on this patent application, see: LEE, In Soo; BAE, Ji Hyae. Nonvolatile Memory Apparatus, Operating Method Thereof, and Data Processing System Having the Same. Filed March 18, 2013 and posted June 19, 2014. Patent URL: http://appft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&u=%2Fnetahtml%2FPTO%2Fsearch-adv.html&r=569&p=12&f=G&l=50&d=PG01&S1=20140612.PD.&OS=PD/20140612&RS=PD/20140612

Keywords for this news article include: Sk Hynix Inc, Information Technology, Information and Data Processing.

Our reports deliver fact-based news of research and discoveries from around the world. Copyright 2014, NewsRx LLC


For more stories covering the world of technology, please see HispanicBusiness' Tech Channel



Source: Information Technology Newsweekly


Story Tools






HispanicBusiness.com Facebook Linkedin Twitter RSS Feed Email Alerts & Newsletters