Patent number 8754480 is assigned to
The following quote was obtained by the news editors from the background information supplied by the inventors: "Power management products for integrated circuits (ICs) such as boost converters, buck converters, low-dropout (LDO) converters, and other power coverters often include one or more power transistors. Such power transistors may consume a relatively large percentage of the total silicon die area of the power converter, and may contribute to relatively high manufacturing costs. Designing the power transistor may also be a complex task, such that design of the power transistor may expend a lot of resources before the design is determined to operate as desired. As a result, making changes to the design of the power transistor may add research and development time and cost, which often causes IC design engineers to over-size the power transistors during the design state in order to compensate for the accumulation of parasitic resistance. Over-sizing the power transistors, however, may unnecessarily increase the manufacturing costs of the die without an associated performance improvement, and in some cases can even result in greater power loss from correspondingly increasing the gate capacitance of the power transistor."
In addition to the background information obtained for this patent, VerticalNews journalists also obtained the inventor's summary information for this patent: "Embodiments of the present invention include a power transistor. The power transistor comprises a drain, a source, and a channel therebetween divided into a plurality of transistor stripes, the plurality of transistor stripes being grouped in a plurality of different groups. The power transistor further comprises a first top metal associated with one of the drain and the source, and a second top metal associated with the other of the drain and the source. The second top metal includes at least one portion that is coupled to different groups of transistor stripes.
"Another embodiment of the present invention includes a power converter. The power converter comprises a first power transistor. The first power transistor comprises a drain, a source, and a channel therebetween, wherein the channel is divided into a plurality of channels that contribute to an overall effective channel width of the first power transistor. The power transistor further comprises a first top metal associated with one of the source and the drain, and a second top metal associated with the other of the source and the drain. The second top metal includes at least a first portion that couples with a first group of the plurality of channels from a first direction, and at least a second portion that couples with a second group of the plurality of channels from a second direction.
"In yet another embodiment of the present invention, a method for determining a layout topology of a power transistor is disclosed. The method comprises estimating a resistance ® of a power transistor based at least in part on a calculation from an equation using a first width, the equation comprising:
".times.e.times..times.e.times. ##EQU00001## wherein
"##EQU00002## p.sub.m is a resistivity of metal layer of the power transistor, p.sub.c is a resistivity of a channel of the power transistor, and w is a width of a plurality of transistor stripes of the power transistor. The method further comprises estimating another resistance of a power transistor based at least in part on a calculation from the equation using a second width of a plurality of transistor stripes of the power transistor, and defining a layout topology of the power transistor using the resistance and the another resistance to determine a quantity and width of transistor stripes for a layout topology of the power transistor responsive to a comparison of the resistance and the another resistance."
URL and more information on this patent, see: Barrow, Jeffrey G.. Low On-Resistance Power Transistor Having Transistor Stripes. U.S. Patent Number 8754480, filed
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