News Column

Patent Issued for Identifying Parasitic Diode(S) in an Integrated Circuit Physical Design

July 2, 2014



By a News Reporter-Staff News Editor at Journal of Engineering -- According to news reporting originating from Alexandria, Virginia, by VerticalNews journalists, a patent by the inventors Kemerer, Douglas W. (Essex Junction, VT); Seibert, Edward W. (Williston, VT); Wang, Lijiang L. (South Burlington, VT), filed on May 15, 2012, was published online on June 17, 2014.

The assignee for this patent, patent number 8756554, is International Business Machines Corporation (Armonk, NY).

Reporters obtained the following quote from the background information supplied by the inventors: "The design of an integrated circuit (IC) that includes transistors and capacitors requires the implant and diffusion of donor or acceptor atoms within oppositely doped regions such as a substrate, nWell, or pWell. While the intent of the design is to create a functional device, these diffusions also form parasitic diodes to the surrounding substrate or Well regions. In early CMOS IC designs, it was always expected that the p-type substrate or pWell regions of the IC would be biased to the lowest potential available on the IC, and that n-type substrate or nWell regions would be biased toward the highest potential on the IC. Under this assumption, any p+ diffusion with an n-type background (or n+ diffusion in a p-type background) parasitic diode would be reverse biased and would not impact circuit function beyond the addition of a depletion capacitance.

"Increasingly, however, as new IC designs push to higher performance, and analog functions are incorporated into ICs, biasing of Well structures between the highest and lowest potentials available has become commonplace. In addition, modern process technologies allow the existence of both nWell and pWell along with substrate on a single IC. And, it has become common for ICs to contain many voltage domains on a single die with data communication between voltage domains. As a result of this increased IC complexity and processing capacity, the risk of unintentionally creating a forward biased parasitic diode between supply domains of an IC during physical design has greatly increased.

"Traditional Design Rule Check (DRC) tools verify that a layout can be manufactured as designed. Traditional Layout vs. Schematic (LVS) tools extract the layout and compare it to the schematic, to ensure a one-to-one correlation. Although DRC and LVS tools may be used independently, they are commonly used in conjunction with each other. Typically, these tools are used iteratively, and the masks are not built until the requirements of both tools are satisfied. While these methods are good at checking the design for adherence to technology ground rules and the equivalence of an IC physical design to its schematics, the detection and analysis of parasitic diode structures that can cause functional problems has not been successfully addressed. Designers have been left to verify their designs using a combination of parasitic netlist extraction and circuit simulation to ascertain whether the circuits function properly over a wide range of static and dynamic power scenarios.

"Current methods and devices require exacting and exhaustive input patterns, and a careful review of the results, both of which are performed manually and are thus subject to human error. As these methods are heavily dependent upon the completeness of the simulation pattern suite, an incomplete or inaccurate extraction process may omit or alter the function of parasitic devices within the design.

"In many cases, the parasitic devices in question would not be extracted as true diodes unless they were manually identified by the designer prior to netlist extraction, which is virtually impossible, as these structures may be incorporated into the design inadvertently. As a result, the escape rate for parasitic forward biased diode structures in the physical design is unacceptably high. The costs of such a high escape rate are expensive redesigns, more frequent product failures, and longer times to market."

In addition to obtaining background information on this patent, VerticalNews editors also obtained the inventors' summary information for this patent: "In a first aspect of the invention, a method comprises tracing terminals of a junction through a circuit layout to associated power supplies to determine their respective defined bias values, and comparing the bias values to determine whether the junction is forward biased.

"In a second aspect of the invention, a method comprises extracting a circuit netlist, tracing terminals of a junction to assigned bias values, and analyzing the assigned bias values for a forward bias condition.

"In a third aspect of the invention, a method comprises identifying well biases and assigning wells into groups. The method further comprises identifying nets having one or more connection points in each of at least two of the groups.

"In a fourth aspect of the invention, a computer program traces from terminals through a circuit layout to associated power supplies to determine defined bias values for each terminal. The method further comprises comparing the defined bias values in order to determine whether the junction is forward biased."

For more information, see this patent: Kemerer, Douglas W.; Seibert, Edward W.; Wang, Lijiang L.. Identifying Parasitic Diode(S) in an Integrated Circuit Physical Design. U.S. Patent Number 8756554, filed May 15, 2012, and published online on June 17, 2014. Patent URL: http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=8756554.PN.&OS=PN/8756554RS=PN/8756554

Keywords for this news article include: International Business Machines Corporation.

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Source: Journal of Engineering