The patent's assignee for patent number 8756468 is
News editors obtained the following quote from the background information supplied by the inventors: "A rapidly increasing complexity of VLSI designs and the associated test costs have generally rendered test data compression a de facto standard. In this test environment, captured responses can be taken through a response compactor, compressing the test responses. While test time and data volume can be thus reduced, the consequent information loss inevitably can reflect a loss in test quality. Certain errors that can be observable in the original scan responses can become unobserved in the compacted responses. Observability loss can be a consequence of multiple errors masking out the effect of each other, producing the expected values in the compressed response, or of the ambiguity induced by unknown response bits (x's) that can take on either binary value upon arbitrary initialization. Un-initialized memory elements such as, e.g., RAMs, multi-cycle paths, or bus contentions in a design can constitute potential sources for unknown values, which may propagate into a scan cell during test. Depending on the structure of the response compactor, these x's can prevent some errors that have been captured in other scan cells from being observed at the compactor outputs.
"Sequential compaction circuitries, such as, e.g, multiple input single registers (MISRs), can be utilized for compressing the scan responses into a signature that can be observed at the end of the test application process. Unknown response bits can corrupt the signature, for example, if they propagate into the MISR. The fact that a single x can corrupt the MISR content can stem from its sequential nature in accumulating its signature. An x-masking circuitry, e.g., one capable of delivering per-scan and/or per-chain replacement of response x's with known constant values based on control bits delivered from Automatic Test Equipment (ATE), can be utilized in order to prevent the corruption of the signature. A costly alternative can be inserting test points to mask x's right at their sources at the expense of area cost and performance degradation. Combinational compaction solutions, e.g., XOR-based, can also be utilized for response compaction. Some of these techniques, for example, can build the response compactor based on fault sensitization information under a particular fault model assumption, while response unknown bit and unmodeled defect coverage issues can be overlooked. Similarly, utilization of a given test set to build compactors, or to reorder x-capturing scan cells can offer improved observability, while dependence on a test set can complicate the implementation of these solutions. Test set and fault model independent response compaction techniques have also been described, which can deliver some x-mitigation capabilities. Further, selective masking/observing of chains, and further optimizations by grouping together of cells that have similar masking requirements over an interval enabled by the clustered behavior of x's can ensure the observation of the targeted faults, while potentially missing unmodeled defects. Correlation among x's can be exploited to reduce the amount of mask control data.
"These compaction techniques can bear a particular resistance characteristic to unknown bits. The density and distribution of x's can determine the test quality delivered by these schemes. In the presence of an x-distribution where the corruption effect of x's is widely spread, combinational compactors typically produce mostly x's at their outputs, while sequential ones with masking-support often produce responses that are over-masked. Thus, in both types of compactors, the fault/defect information in x-free scan cells can be compromised, resulting in poor scan cell observability, and, hence, degradation in test pattern effectiveness. A test pattern inflation and hence a test cost increase may ensue upon attempts on restoring the compromised quality levels. Further, high quality screening of chips may utilize aggressive solutions such as faster-than-at-speed testing, which can generate responses with high density of unknown x's.
"In an effort to cope with increasing test costs, test data compression solutions can be employed, wherein a few number of scan-in channels drive a larger number of internal scan chains through a decompression block, while the responses collected from the internal scan chains can be taken through a compactor block that drives a fewer number of scan-out channels. Driving a larger number of internal scan chains from a fewer number of scan channels can reduce the depth of the scan chains, decreasing the number of shift (e.g., scan) operations per scan pattern, and hence shortening the test application time.
"Certain logic blocks, such as RAMs or tri-state buses, and setup requirement violator paths may produce values that are unknown during simulation time, and are known only after the chip has been powered up, where these values can change from one chip to another. Test patterns may propagate these unknown bits (x's) to the outputs, capture them in scan cells, and produce response patterns with x's. While the observation of individual known (non-x) bits in the response can assist with an indication as to whether the chip under test is defective, a compression of x's and non-x's altogether through a response compactor can weaken this screening process. The ambiguity induced by the response x's results in the loss of some of the known bits, which can have otherwise manifested the effect of the defects in the chip under test. Test quality, may be degraded as a result.
"Accordingly, there can be a need to address and/or overcome at least some of the above described deficiencies and issues."
As a supplement to the background information on this patent, VerticalNews correspondents also obtained the inventor's summary information for this patent: "Such need can be addressed with the exemplary embodiments of the present disclosure of architecture, apparatus, methods, and computer-accessible medium for masking unknown bits.
"For example, according to exemplary embodiments of the present disclosure, apparatus, methods, and computer-accessible medium for a toggle-masking procedure configured to mask some or all of the unknown x's and minimize the over-masked known bits for clustered distribution of unknown bits can be provided. In certain exemplary embodiments of the present disclosure, it is possible to utilize an exemplary toggle-masking framework as a foundation, and transform this exemplary solution into an x-filter that allows a certain number/distribution of x's to pass, in order to further improve the observability levels. According to the exemplary toggle-masking scheme of the exemplary embodiment of the present disclosure can be paired and/or utilized with another exemplary technique, such as, e.g., an x-canceling multiple-input signature register (MISR), which can be used to cancel the x's in the signature via post-processing operations. According to further exemplary embodiments of the present disclosure, it is possible to utilize the x-filter with different versions of x-canceling MISR, which may be subject to test time increase and/or observability loss with high x-density responses. Thus, in certain exemplary embodiments of the present disclosure, it is possible to provide an x-filter that can adjust the number/distribution of x in-flow into the MISR, which can provide a control over test time and observability, e.g., offering a wide spectrum of tradeoff solutions for the designers.
"An exemplary toggle-based masking procedure that can be used to deliver very high observability levels in the case of clustered x distributions can be provided in certain exemplary embodiments. The exemplary procedure can, for example, assign a single-bit state to each chain, dictating whether the chain will be masked or observed. For example, a clustered distribution of x's can enable an infrequent switching of state information, minimizing the amount of mask data that cab selectively toggles the state of chains. Thus, few mask channels may typically be used to control the proposed masking hardware, which can enable the blocking of the x's while over-masking a small number of non-x bits. A capability to mask the x's can facilitate the use of a MISR in conjunction, and can thus eliminate the need for a scan-out channel, translating into enhanced parallelism in multi-site testing. Exemplary results on industrial test cases can indicate that the exemplary masking procedure can be capable of minimizing or even eliminating over-masking, which can deliver near-optimal test quality levels.
"For example, according to further exemplary embodiments of the present disclosure, it is possible to use an exemplary procedure targeted for clustered distributions of x's, which can be a typical end-result of x-sources residing in close proximity. The exemplary procedure according to the present disclosure can facilitate masking a number of consecutive bits in chains by specifying, e.g., the beginning and the end locations of the x-run via the control of dedicated mask channels. The chains can be assigned a single-bit state that can dictate, for example, whether the chain is masked or observed, and the state can be toggled to switch between two states so as to mask the x's while minimizing over-masked non-x bits. It can be the case that the state of at most a single chain can be toggled in any shift cycle, which can enable a continuous-flow and simple masking circuitry controlled by log (n+1) channels for n scan chains. In exemplary experiments utilizing certain exemplary embodiments of the present disclosure on an exemplary industrial test case, the exemplary masking procedure can minimize or even eliminate over-masking, which can deliver, for example, near-perfect test quality levels.
"As the exemplary procedure can be configured to mask the x's, the use of an accompanying MISR can be facilitated, preferably eliminating the use of scan-out channels. The replacement of scan-out channels with mask channels can enhance parallelism in multi-site testing. Further, the same set of mask channels can be shared among the dies being tested in parallel, but a distinct set of scan-out channels may need to be allocated for each die. Thus, eliminating scan-out channels can allow for the test of a larger number of dies in multi-site testing, e.g., delivering test time reductions.
"According to exemplary embodiments of the present disclosure, apparatus, methods, and computer-accessible medium for a toggle-based masking procedure that can facilitate a delivery of very high observability levels in the case of clustered x distributions. In certain exemplary embodiments, an exemplary block can associate a single-bit state with each scan chain that dictates whether the chain is masked or observed. Clustered distribution of x's can reduce the need to update the state of scan chains. The exemplary block can enable the selection of at most one chain in every shift cycle, and can toggle its state to switch between the mask and observe states. According to certain exemplary embodiments of the present disclosure, it is possible to also provide not only an exemplary ILP formulation but also a computationally efficient exemplary greedy heuristic to minimize over-masking while blocking the x's. The exemplary procedure, by blocking the x's, can facilitate the use of a MISR in conjunction, and can thus eliminate the need for a scan-out channel, enhancing parallelism in multi-site testing.
"Further, according to certain exemplary embodiments of the present disclosure, methods, computer-accessible medium, and systems can be provided for toggle-based masking of at least one scan chain. For example, it is possible to obtain previous masking information regarding at least one scan chain associated with a previous cycle; and mask the at least one chain for a present cycle based on the previous masking information. In further exemplary embodiment, it is also possible to change the masking of the at least one scan chain, e.g., while maintaining the masking of all other scan chains of the at least one scan chain.
"According to further exemplary embodiments of the present disclosure, it is possible to change the masking of at most one scan chain (or a plurality of scan chains, e.g., 2, 3, etc.) in the present cycle. It is also possible to provided a decoding arrangement which can be configured to receive an address associated with each scan chain for which the masking is to be changed.
"According to further exemplary embodiments of the present disclosure, it is possible to analyze a distribution of at least one unknown bit in a response pattern; and perform the masking by masking the unknown bit(s) and a subset of known bits. In addition, it is possible to minimize a number of masked known bits. In certain exemplary embodiments, the minimization procedure can be performed by the processing or computing (e.g., hardware) arrangement using linear programming.
"In certain exemplary embodiments, the minimization procedure can be performed by the processing or computing arrangement using at least one integer linear programming technique (ILP). In certain exemplary embodiments, the ILP can be provided such that a number of scan chains selected includes a maximum number of scan chains. According to additional certain exemplary embodiments, the ILP can be provided to mask at least one unknown bit and/or all unknown bits. In certain exemplary embodiments, the ILP can include an optimization criterion configured to minimize the number of masked known bits.
"According to particular exemplary embodiments of the present disclosure, the minimization procedure can be performed by the processing of the present disclosure arrangement using a greedy procedure. For example, the greedy procedure can include (i) masking all unknown bits and/or (ii) iteratively selecting and masking at least one known bit to satisfy a constraint of selecting at most a maximum number of scan chains in a cycle. For example, the known bits can be selected by the greedy procedure to maximally reduce decision changes from one cycle to a next cycle.
"According to particular exemplary embodiments of the present disclosure, prior to using the greedy procedure, the exemplary embodiments can allow at least one lonely-x to pass, the at least one lonely-x selected from among a plurality of lonely-x's based at least in part on a quantity of toggles associated with the at least one lonely-x. In another exemplary embodiment the allowing can be performed on the at least one lonely-x until a pre-determined x-budget is reached.
"These and other objects, features and advantages of the present disclosure will become apparent upon reading the following detailed description of embodiments of the present disclosure, and the appended claims."
For additional information on this patent, see: Sinanoglu, Ozgur. Architecture, System, Method, and Computer-Accessible Medium for Toggle-Based Masking. U.S. Patent Number 8756468, filed
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