News Column

Patent Application Titled "Vectorization of Bit-Level Netlists" Published Online

July 1, 2014



By a News Reporter-Staff News Editor at Information Technology Newsweekly -- According to news reporting originating from Washington, D.C., by VerticalNews journalists, a patent application by the inventors Baumgartner, Jason R. (Austin, TX); German, Steven M. (Wayland, MD), filed on December 10, 2012, was made available online on June 19, 2014.

The assignee for this patent application is International Business Machines Corporation.

Reporters obtained the following quote from the background information supplied by the inventors: "In integrated circuit and hardware design, verification refers to the process of proving that a design satisfies its specification. For example, digital logic circuits implement a logic function and represent the core of any computing processing unit. These designs are often of substantial complexity, comprising a diversity of bit-level control logic, data paths, and performance-related artifacts including pipelining, multi-threading, out-of-order execution, and power-saving techniques. Memory arrays are ubiquitous in hardware designs, representing caches, main memory, lookup tables, and the like.

"Before a logic design is constructed in real hardware, its design is tested and the operation thereof verified against a design specification. Typically, the specification of a verification problem includes a netlist-based representation of the design and a set of expected values for specified nets under specified conditions. However, verification techniques generally require computational resources which are exponential with respect to the size of the design under test. In particular, many formal analysis techniques require exponential resources with respect to the number of state elements in the design under test. Thus, it's often desirable to reduce the complexity of a design under verification. For example, abstraction techniques may be used to reduce memory array sizes (e.g., to reduce the number of rows which need to be modeled), to enable reductions in the size of the netlist under verification, and thereby reduce verification complexity."

In addition to obtaining background information on this patent application, VerticalNews editors also obtained the inventors' summary information for this patent application: "According to one aspect of the present disclosure a method and technique for vectorization of bit-level netlists is disclosed. The method includes: receiving a bit-level netlist defining a plurality of registers; analyzing propagation of read data associated with the registers through logic of the bit-level netlist; and forming a plurality of vector-level bundles of registers based on the propagation of read data through the logic, wherein the plurality of vector-level bundles differ based on differences in references to memory arrays of the bit-level netlist by respective registers of the vector-level bundles.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS

"For a more complete understanding of the present application, the objects and advantages thereof, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which:

"FIG. 1 is an embodiment of a network of data processing systems in which the illustrative embodiments of the present disclosure may be implemented;

"FIG. 2 is an embodiment of a data processing system in which the illustrative embodiments of the present disclosure may be implemented;

"FIG. 3 is a diagram illustrating an embodiment of a data processing system for vectorization of bit-level netlists in which illustrative embodiments of the present disclosure may be implemented;

"FIG. 4 is a diagram depicting an embodiment of pseudo-code for performing vectorization of bit-level netlists according to the present disclosure;

"FIG. 5 is a diagram depicting another embodiment of pseudo-code for performing vectorization of bit-level netlists according to the present disclosure;

"FIG. 6 is a diagram depicting another embodiment of pseudo-code for performing vectorization of bit-level netlists according to the present disclosure;

"FIG. 7 is a flow diagram illustrating an embodiment of a method for vectorization of bit-level netlists according to the present disclosure;

"FIG. 8 is a flow diagram illustrating another embodiment of a method for vectorization of bit-level netlists according to the present disclosure; and

"FIG. 9 is a flow diagram illustrating another embodiment of a method for vectorization of bit-level netlists according to the present disclosure."

For more information, see this patent application: Baumgartner, Jason R.; German, Steven M. Vectorization of Bit-Level Netlists. Filed December 10, 2012 and posted June 19, 2014. Patent URL: http://appft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&u=%2Fnetahtml%2FPTO%2Fsearch-adv.html&r=236&p=5&f=G&l=50&d=PG01&S1=20140612.PD.&OS=PD/20140612&RS=PD/20140612

Keywords for this news article include: Information Technology, Information and Data Processing, International Business Machines Corporation.

Our reports deliver fact-based news of research and discoveries from around the world. Copyright 2014, NewsRx LLC


For more stories covering the world of technology, please see HispanicBusiness' Tech Channel



Source: Information Technology Newsweekly


Story Tools






HispanicBusiness.com Facebook Linkedin Twitter RSS Feed Email Alerts & Newsletters