News Column

Patent Application Titled "Package Having Thermal Compression Flip Chip (Tcfc) and Chip with Reflow Bonding on Lead" Published Online

July 3, 2014



By a News Reporter-Staff News Editor at Politics & Government Week -- According to news reporting originating from Washington, D.C., by VerticalNews journalists, a patent application by the inventors Aldrete, Manuel (San Diego, CA); Shah, Milind P. (San Diego, CA); Bchir, Omar J. (San Diego, CA); Jomaa, Houssam W. (San Diego, CA); Kim, Chin-Kwan (San Diego, CA), filed on December 7, 2012, was made available online on June 19, 2014.

The assignee for this patent application is QUALCOMM Incorporated.

Reporters obtained the following quote from the background information supplied by the inventors: "A thermal compression bonding process is a process used to assemble/package a flip chip, die or semiconductor device to a packaging substrate. Such a flip chip is often referred to as a thermal compression flip chip (TCFC). Thermal compression bonding processes provide several advantages over traditional bonding processes. For example, thermal compression bonding processes are generally more accurate than other solder bonding processes. Thus, thermal compression bonding processes are ideal when using fine pitch traces on a substrate (e.g., less than 100 microns (.mu.n)). In contrast, other solder bonding processes are limited to a bonding pitch that is greater than 100 microns (.mu.m). Thus, TCFCs are typically higher density chips than chips using other bonding processes.

"FIG. 1 illustrates an example of a chip/die coupled to a substrate using a thermal compression bonding process. As shown in FIG. 1, a chip 102 is coupled to a substrate 100. There are several electrical connections between the chip 102 and the packaging substrate 100. These electrical connections may be defined as under bump metallization (UBM) structures, solder and traces. These electrical connections are conceptually represented by components 104. There is also a non-conductive paste (NCP) 106 between the chip 102 and the substrate 100. The NCP 106 provides a protective layer that covers the electrical connections 104 between the chip 102 and the substrate 100.

"FIGS. 2-4 illustrate an example of a sequence of how a chip/die may be assembled to a package by using a thermal compression bonding process. The top portion of FIG. 2 illustrates a package 200 that a die may be mounted on using a thermal compression bonding process. The package 200 includes a packaging substrate 202 and several traces 203a-c. FIG. 2 also illustrates a non-conductive paste (NCP) 201, which has been dispensed on top of the traces 203a-c. The NCP 201 is dispensed before a thermal compression bonding process is done.

"The bottom portion of FIG. 2 illustrates a die 208 that is being coupled to the package 200. As shown in FIG. 2, the die 208 is coupled to a heater 210. The die 208 includes several bumps 204a-e. Each of the bumps 204a-c respectively includes copper pillars 205a-c. Each bumps 204a-c may also respectively include solders 206a-c.

"FIG. 3 illustrates the thermal compression bonding process being applied to the die 208. Specifically, FIG. 3 illustrates that after the die 208 has been place on the packaging substrate 202, and the bumps 204a-c are properly aligned with the traces 203a-c, the heater 210 heats the die 208 and the bumps 204a-c, thereby coupling the die 208 to the package 200. FIG. 4 illustrates the die 208 coupled to the package 200. Specifically, FIG. 4 illustrates the heater 210 being removed from the die 208 once the die 208 has been coupled to the package 200 using a thermal compression bonding process. In some implementations, pressure may also be applied in order to couple the die 208 to the package 200.

"FIG. 5 illustrates several TCFCs coupled to a package. As shown in FIG. 5, the package 500 includes a substrate 502, a first thermal compression flip chip (TCFC) 504, a second TCFC 506, and a third TCFC 508. In some implementations, the package 500 is an integrated circuit package, such as a System-in-Package (SiP). Each of the first, second, and third chips 504-508 has been coupled to the substrate 502 using a thermal compression bonding process. One of the characteristics of a thermal compression bonding process is that each chip must be bonded to the substrate one at a time. That is, each TCFC must be placed on the substrate and heated before another TCFC can be placed on the substrate and heated. In other words, TCFCs are coupled to a package in series and not in parallel. This is problematic because the process of coupling several TCFCs to a package can be expensive if each bonding process must be done in series.

"Moreover, the thermal compression bonding process can take a lot of time. In fact, relative to other bonding processes, the thermal compression bonding process has a very low unit per hour (UPH) value. A UPH value specifies how many units of something (e.g., die) can be produced/created in a given amount of time. Thus, despite the fact that a thermal compression bonding process can be used with substrates having fine pitch traces, using such a process may not be desirable, where it may not be needed, due to the cost and time associated with coupling several chips to a package.

"Therefore, there is a need for a package that includes several chips, where the package can be manufactured very quickly, efficiently and at a lower cost than exclusively using a thermal compression bonding process."

In addition to obtaining background information on this patent application, VerticalNews editors also obtained the inventors' summary information for this patent application: "Various features relate to a package having a thermal compression flip chip (TCFC) and a chip with reflow bonding on lead.

"A first example provides an integrated circuit (IC) package that includes a substrate, a first die and a second die. The substrate includes a first set of traces and a second set of traces. The first set of traces has a first pitch. The second set of traces has a second pitch. The first pitch is less than the second pitch. In some implementations, a pitch defines a center to center distance between two neighboring traces. The first die is coupled to the substrate by a thermal compression bonding process. The first die is coupled to the first set of traces of the substrate. The second die is coupled to the substrate by a reflow bonding process. The second die is coupled to the second set of traces of the substrate.

"According to one aspect, the IC package includes a copper bond on lead located between the second die and the substrate. The copper bond on lead provides an electrical path for the die. In some implementations, the IC package further includes a non-conductive epoxy layer located between the first die and the substrate. The non-conductive epoxy layer provides a protective layer for a joint between the first die and the substrate.

"According to another aspect, the IC package further includes a third die coupled to the substrate by the reflow bonding process. In some implementations, the reflow bonding process is concurrently applied to the second die and the third die after the first die is coupled to the substrate by the thermal compression bonding process.

"According to yet another aspect, the first pitch is a pitch of less than 100 microns (.mu.m) and the second pitch is a pitch of more than 100 microns (.mu.m).

"A second example provides a method for manufacturing an integrated circuit (IC) package. The method couples a first die to a substrate of the IC package by a thermal compression bonding process. The method further couples a second die to the substrate of the IC package by a reflow bonding process.

"According to one aspect, the substrate has a first set of traces and a second set of traces. In some implementations, the first set of traces has a first pitch and the second set of traces has a second pitch. The first pitch is less than the second pitch. In some implementations, a pitch defines a center to center distance between two neighboring traces. In some implementations, the first pitch is pitch of 100 microns (.mu.m) or less and the second pitch is a pitch of more than 100 microns (.mu.m).

"According to another aspect, coupling the first die to the substrate includes coupling the first die to the first set of traces of the substrate. In some implementations, coupling the second die to the substrate includes coupling the second die to the second set of traces of the substrate.

"According to yet another aspect, the method further includes coupling a third die to the substrate of the IC package by the reflow bonding process, where the second die and the third die are coupled to the substrate in parallel during the same reflow bonding process. In some implementations, the reflow bonding process is concurrently applied to the second die and the third die after the first die is coupled to the substrate by the thermal compression bonding process. In some implementations, the thermal compression bonding process has a lower units per hour (UPH) value than the UPH value of the reflow bonding process. In some implementations, the UPH value defines a number of units that can be manufactured during a given amount of time.

"According to one aspect, the first die has a first density connection with the substrate. The second die has a second density connection with the substrate. The second density connection is less than the first density connection.

"A third example provides an apparatus for manufacturing an integrated circuit (IC) package. The apparatus includes means for coupling a first die to a substrate of the IC package by a thermal compression bonding process. The apparatus also includes means for coupling a second die to the substrate of the IC package by a ram bonding process.

"According to one aspect, the substrate has a first set of traces and a second set of traces. The first set of traces has a first pitch and the second set of traces has a second pitch. The first pitch is less than the second pitch. In some implementations, a pitch defines a center to center distance between two neighboring traces. In some implementations, the first pitch is a pitch of 100 microns (.mu.m) or less and the second pitch is a pitch of more than 100 microns (.mu.m).

"According to another aspect, the apparatus further includes means for coupling a third die to the substrate of the IC package by the reflow bonding process. In some implementations, the second die and the third die are coupled to the substrate in parallel during the same reflow bonding process. In some implementations, the reflow bonding process is concurrently applied to the second die and the third die after the first die is coupled to the substrate by the thermal compression bonding process.

"According to another aspect, the thermal compression bonding process has a lower units per hour (UPH) value than the UPH value of the reflow bonding process. In some implementations, the UPH value defines a number of units that can be manufactured during a given amount of time.

"A fourth example provides a computer readable storage medium comprising one or more instructions for manufacturing an integrated circuit (IC) package, which when executed by at least one processor, causes the at least one processor to couple a first die to a substrate of the IC package by a thermal compression bonding process, and couple a second die to the substrate of the IC package by a reflow bonding process.

"According to one aspect, the substrate has a first set of traces and a second set of traces. The first set of traces has a first pitch and the second set of traces has a second pitch. The first pitch is less than the second pitch. In some implementations, a pitch defines a center to center distance between two neighboring traces. In some implementations, the first pitch is a pitch of 100 microns (.mu.m) or less and the second pitch is a pitch of more than 100 microns (.mu.m).

DRAWINGS

"Various features, nature and advantages may become apparent from the detailed description set forth below when taken in conjunction with the drawings in which like reference characters identify correspondingly throughout.

"FIG. 1 illustrates a thermal compression flip chip coupled to a packaging substrate.

"FIG. 2 illustrates a thermal compression flip chip being attached to a packaging substrate.

"FIG. 3 illustrates a thermal heating being applied to bond a thermal compression flip chip to a packaging substrate.

"FIG. 4 illustrates a heater being removed from a thermal compression flip chip (die).

"FIG. 5 illustrates a package that includes several thermal compression flip chips.

"FIG. 6 illustrates a package that includes a thermal compression flip chip and several reflow bonding on lead chips.

"FIG. 7 illustrates a flow diagram of a method for manufacturing a package that includes a thermal compression flip chip and a reflow bonding on lead chip.

"FIGS. 8A-8C illustrate a sequence for manufacturing a package that includes a thermal compression flip chip and several reflow bonding on lead chips.

"FIGS. 9A-9B illustrate a flow diagram of a detailed method for manufacturing a package that includes a thermal compression flip chip and a reflow bonding on lead chip.

"FIG. 10 illustrates various electronic devices that may integrate the IC described herein."

For more information, see this patent application: Aldrete, Manuel; Shah, Milind P.; Bchir, Omar J.; Jomaa, Houssam W.; Kim, Chin-Kwan. Package Having Thermal Compression Flip Chip (Tcfc) and Chip with Reflow Bonding on Lead. Filed December 7, 2012 and posted June 19, 2014. Patent URL: http://appft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&u=%2Fnetahtml%2FPTO%2Fsearch-adv.html&r=6012&p=121&f=G&l=50&d=PG01&S1=20140612.PD.&OS=PD/20140612&RS=PD/20140612

Keywords for this news article include: QUALCOMM Incorporated.

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