News Column

Patent Application Titled "Bandgap Reference Circuit" Published Online

July 3, 2014



By a News Reporter-Staff News Editor at Politics & Government Week -- According to news reporting originating from Washington, D.C., by VerticalNews journalists, a patent application by the inventors Iguchi, Taiki (Kanagawa, JP); Akebono, Sachio (Kanagawa, JP); Hirono, Daisuke (Kanagawa, JP); Makigawa, Kiyoshi (Kanagawa, JP); Jeong, Moonjae (Kanagawa, JP), filed on November 13, 2013, was made available online on June 19, 2014.

The assignee for this patent application is Sony Corporation.

Reporters obtained the following quote from the background information supplied by the inventors: "The present disclosure relates to a bandgap reference circuit.

"Nowadays, along with miniaturizations and high integrations of semiconductor integrated circuits, circuits are requested to be operated at a low voltage, and thus integrated circuit manufacturers including the applicant have responded to the such a request. The low-voltage drive is of course also requested for a bandgap reference circuit that generates a reference voltage.

"It should be noted that Japanese Patent Application Laid-open No. Hei 11-45125 (hereinafter, referred to as Patent Document 1) is a related art document that discloses a technique that is considered to be close to the present disclosure. Patent Document 1 discloses a technique for enabling an operation to be made at 1.25 V or less by setting a voltage that is output from a reference voltage generation circuit and is less dependent on a temperature and power supply voltage to an arbitrary value within a power supply voltage."

In addition to obtaining background information on this patent application, VerticalNews editors also obtained the inventors' summary information for this patent application: "FIG. 8 is a circuit diagram of a bandgap reference circuit 801 of the related art disclosed in Patent Document 1.

"A source of a first PMOSFET 102 as a P-channel MOSFET (hereinafter, abbreviated to 'PMOSFET', and N-channel MOSFET will similarly be abbreviated to 'NMOSFET') is connected to a power supply node, and a drain thereof is connected to a first resistor R103. The other end of the first resistor R103 is connected to an anode of a first diode 104. A cathode of the first diode 104 is connected to a ground node. A second resistor R105 is connected between the drain of the first PMOSFET 102 and the ground node while being connected in parallel with the first resistor R103 and the first diode 104 connected in series.

"A source of a second PMOSFET 106 is connected to the power supply node, and a drain thereof is connected to an anode of a second diode 107. A cathode of the second diode 107 is connected to the ground node. A third resistor R108 is connected between the drain of the second PMOSFET 106 and the ground node while being connected in parallel with the second diode 107.

"Here, resistance values of the second resistor R105 and the third resistor R108 are the same.

"A source of a third PMOSFET 109 is connected to the power supply node, and a drain thereof is connected to one end of a fourth resistor R110 and also to a reference voltage output terminal Vout. The other end of the fourth resistor R110 is connected to the ground node.

"A non-inverting input terminal of an operational amplifier 111 is connected to the drain of the first PMOSFET 102.

"An inverting input terminal of the operational amplifier 111 is connected to the drain of the second PMOSFET 106.

"An output terminal of the operational amplifier 111 is connected to gates of the first PMOSFET 102, the second PMOSFET 106, and the third PMOSFET 109, and a gate voltage is commonly controlled by the operational amplifier 111. In other words, the three PMOSFETs constitute a current mirror circuit.

"As can be understood from FIG. 8, the first diode 104 is formed by connecting a plurality of diodes in parallel unlike the second diode 107. Since the bandgap reference circuit 801 is constituted of an integrated circuit, the diodes forming the first diode 104 and the second diode 107 are formed by the same production process (same electrical characteristics).

"The diode includes elements of an ideal diode and a resistor. Therefore, since combined resistance values differ for the first diode 104 and the second diode 107, current densities differ.

"A potential difference caused by the difference in the current densities of the first diode 104 and the second diode 107 is converted into a current I2a having positive temperature characteristics by the first resistor R103.

"On the other hand, both end voltages of the second diode 107 are converted into a current I1a having negative temperature characteristics by the third resistor R108.

"The non-inverting input terminal of the operational amplifier 111 is set as a voltage point VA, and the inverting input terminal thereof is set as a voltage point VB.

"Since the operational amplifier 111 equivalently controls the first PMOSFET 102 connected to the voltage point VA and the second PMOSFET 106 connected to the voltage point VB, potential differences of the second resistor R105 and the third resistor R108 become the same. In addition, since the resistance values of the second resistor R105 and the third resistor R108 are the same, a current I2b flowing through the second resistor R105 and a current I1b flowing through the third resistor R108 also become the same.

"The third PMOSFET 109 constituting a constant current source outputs a sum current of the currents I2a and I2b by the current mirror circuit. Since the sum current has opposite temperature characteristics, the voltage caused in the fourth resistor R110 becomes a reference voltage having no temperature characteristics.

"By using the technique disclosed in Patent Document 1, the bandgap reference circuit 801 with which a reference voltage having no temperature characteristics can be obtained can be realized. However, the circuit disclosed in Patent Document 1 has a quasi-stabilization point as will be described later. Therefore, a startup circuit for eliminating an erroneous stabilization at the quasi-stabilization point becomes necessary.

"An example of the startup circuit is shown in FIG. 9.

"FIG. 9 is a circuit diagram of a bandgap reference circuit 901 of the related art including the startup circuit. The bandgap reference circuit 901 shown in FIG. 9 has a structure in which a startup circuit 900 is added to the bandgap reference circuit 801 shown in FIG. 8.

"The same current as the third PMOSFET 109 is caused to flow through a PMOSFET 902 of the startup circuit 900 to thus cause a voltage in a resistor R903. An inter-terminal voltage of the resistor R903 is input to a gate of a PMOSFET 904 and a gate of an NMOSFET 905 constituting an inverter. A drain of the PMOSFET 904 and a drain of the NMOSFET 905 are connected to a gate of an NMOSFET 906.

"Since the inter-terminal voltage of the resistor R903 is almost the same as the ground potential at a time the bandgap reference circuit 901 is activated, the inverter becomes a high potential, and the NMOSFET 906 is put to an ON state. After that, the inverter shifts to a low potential as the inter-terminal voltage of the resistor R903 increases, and the NMOSFET 906 is put to an OFF state. In other words, the circuit is stabilized by dropping the voltage controlling the power supply source to the ground potential during an unstable state at the time the circuit is activated.

"However, provision of the startup circuit 900 leads to an increase in the number of components to thus result in an enlargement of a circuit scale in the integrated circuit. Moreover, depending on a production process of the integrated circuit, it may be difficult to incorporate the startup circuit 900.

"In view of the circumstances as described above, there is a need for a bandgap reference circuit that does not have a quasi-stabilization point and outputs a stable voltage.

"According to an embodiment of the present disclosure, there is provided a bandgap reference circuit including: a first PMOSFET having a source connected to a power supply node; a first resistor having one end connected to a drain of the first PMOSFET; a first diode connected to the other end of the first resistor and a ground node; a second PMOSFET having a source connected to the power supply node; a second diode connected to a drain of the second PMOSFET and the ground node; a second resistor connected between the drain of the first PMOSFET and the ground node; and a third resistor connected between the drain of the second PMOSFET and the ground node.

"The bandgap reference circuit also includes: a third PMOSFET having a source connected to the power supply node and a drain connected to an output node of a reference voltage; a fourth resistor connected between the drain of the third PMOSFET and the ground node; and an operational amplifier having a non-inverting input terminal connected to the drain of the first PMOSFET and an inverting input terminal connected to the drain of the second PMOSFET, to which a voltage higher than a voltage supplied to the non-inverting input terminal may be supplied, an output voltage of the operational amplifier being applied to each gate of the first PMOSFET, the second PMOSFET, and the third PMOSFET.

"According to the embodiment of the present disclosure, a bandgap reference circuit that does not have a quasi-stabilization point and outputs a stable voltage can be provided without providing a startup circuit.

"These and other objects, features and advantages of the present disclosure will become more apparent in light of the following detailed description of best mode embodiments thereof, as illustrated in the accompanying drawings.

BRIEF DESCRIPTION OF DRAWINGS

"FIG. 1 is a circuit diagram of a bandgap reference experiment circuit in which an experiment for explaining a principle of the present disclosure has been performed;

"FIG. 2 is a graph showing a result of the experiment for explaining the principle of the present disclosure;

"FIG. 3 is a circuit diagram of a bandgap reference circuit according to a first embodiment of the present disclosure;

"FIG. 4 is a graph showing a result of an experiment performed on the bandgap reference circuit according to the first embodiment of the present disclosure;

"FIG. 5 is a circuit diagram of a bandgap reference circuit according to a second embodiment of the present disclosure;

"FIG. 6 is a circuit diagram of a bandgap reference circuit according to a third embodiment of the present disclosure;

"FIG. 7 is a circuit diagram of a bandgap reference circuit according to a fourth embodiment of the present disclosure;

"FIG. 8 is a circuit diagram of a bandgap reference circuit of the related art; and

"FIG. 9 is a circuit diagram of a bandgap reference circuit of the related art including a startup circuit."

For more information, see this patent application: Iguchi, Taiki; Akebono, Sachio; Hirono, Daisuke; Makigawa, Kiyoshi; Jeong, Moonjae. Bandgap Reference Circuit. Filed November 13, 2013 and posted June 19, 2014. Patent URL: http://appft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&u=%2Fnetahtml%2FPTO%2Fsearch-adv.html&r=5551&p=112&f=G&l=50&d=PG01&S1=20140612.PD.&OS=PD/20140612&RS=PD/20140612

Keywords for this news article include: Sony Corporation.

Our reports deliver fact-based news of research and discoveries from around the world. Copyright 2014, NewsRx LLC


For more stories covering the world of technology, please see HispanicBusiness' Tech Channel



Source: Politics & Government Week


Story Tools






HispanicBusiness.com Facebook Linkedin Twitter RSS Feed Email Alerts & Newsletters