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The following quote was obtained by the news editors from the background information supplied by the inventors: "Radio Frequency (RF) transceivers are mainly used to shift a RF input spectrum down in frequency in order to reduce the sampling frequency of digital channel decoders.
"Frequency division is a well-known concept, especially in the field of telecommunications, which may be used to reduce the frequency of a signal.
"Such frequency division is typically used in the generation of a Local Oscillator (LO) signal and makes use of a mixer which employs a LO as a frequency selector. The spectral purity of the LO can be an important consideration for effective RF signal reception.
"A parameter typically used to quantify the spectral purity of a LO is the phase noise (expressed in dB/Hz), wherein a good LO signal will have a low phase noise.
"In order to achieve a good phase noise, conventional systems use a low noise VCO (Voltage Controlled Oscillator), which enables frequency tuning
"However, modern telecommunication systems are required to deal with a very wide tuning range (for example, a range where the maximum frequency divided by the minimum frequency of the range is greater than two).
"A conventional VCO cannot typically be tuned over such a wide range of frequencies without a reduction in the phase noise performance (i.e. without an increase in the phase noise). For this reason, it is known to place a programmable frequency divider between a VCO and a mixer in order to extend the tuning range. Such a frequency divider is often referred to as a LO chain and typically has two outputs (I and Q), balanced duty cycles, and low output noise. However, such features increase the design complexity of a frequency divider. The higher the complexity, the more difficult it is to achieve an acceptable trade-off between noise and power consumption.
"A way to achieve very low phase noise with low power consumption is to 're-clock' the output of a frequency divider by a higher frequency, as shown in FIG. 1. Here, the first and second outputs of a LO chain 10 are provided to first 12 and second 14 data flip-flops, respectively. The input reference clocking signal F.sub.IN provided to the LO chain 12 is also provided to the clock input terminal of the first 12 and second 14 data flip-flops. Thus, it can be seen how the I and Q outputs of the LO chain 12 are clocked by the input reference clocking signal F.sub.IN (which is of a higher frequency than the I and Q outputs). Accordingly, this technique is known as 're-clocking' and enables the reduction of accumulated jitter in the LO chain frequency divider.
"This known technique of re-clocking poses the problem of how to re-clock (i.e. 're-time' or align) the LO chain output signal with a low noise (or low jitter) high frequency reference clocking signal. Conventional approaches assume that the operating frequency (i.e. the frequency of the reference clocking signal) is low enough to enable ideal control of the phase of both the re-clocking signal (i.e. the reference clocking signal) and the frequency divider output signal. If this is not the case, then metastability in the re-clocking flip-flop(s) may occur, as illustrated in FIGS. 2A-2B.
"As shown in FIG. 2A illustrated, if the flip-flop data input D outside of a brief time window during which the reference clocking signal F.sub.IN rises, the output Q of the flip-flop correctly takes on the value of data input D without any instability. However, as shown in FIG. 2B, if the flip-flop data input D changes at the same time the reference clocking signal F.sub.IN rises (or within a small time window surrounding the time at which the reference clocking signal F.sub.IN rises), the output Q may become undefined. This is because the delay between both signals is less than the minimum set-up/hold time of the flip-flop."
In addition to the background information obtained for this patent application, VerticalNews journalists also obtained the inventor's summary information for this patent application: "According to an embodiment of the invention, there is provided a local oscillator signal generation circuit according to independent claim 1.
"Compared to conventional approaches, embodiments may exhibit reduced power consumption whilst also achieving reduced phase noise.
"According to an embodiment of the invention, there is provided a method of generating a local oscillator signal for a frequency divider circuit according to claim 9.
"Embodiments may be used in broadband receiver applications, such as analog TV broadcasting, digital TV broadcasting, cable TV broadcasting, satellite broadcasting, UMTS, etc
"Embodiment may be applicable to any application where two edges need to be aligned for re-clocking purposes.
BRIEF DESCRIPTION OF THE DRAWINGS
"Preferred embodiments of the present invention will now be described, by way of example only, with reference to the following drawings in which:
"FIG. 1 illustrates a conventional re-clocking arrangement wherein the outputs of a LO chain are clocked by the input reference clocking signal of the LO chain;
"FIG. 2a is a timing diagram illustrating good alignment of the data input and the input reference clocking signal for a convention re-clocking arrangement like that of FIG. 1;
"FIG. 2b is a timing diagram illustrating poor alignment of the data input and the input reference clocking signal for a convention re-clocking arrangement like that of FIG. 1;
"FIG. 3 is a schematic block diagram of a local oscillator signal generation circuit according to an embodiment;
"FIG. 4 illustrate the transfer function of the embodiment of FIG. 3;
"FIG. 5 illustrates how the transfer function shown in FIG. 4 can be seen as a mask on a reference clock signal in the time domain;
"FIG. 6 shows the amplitude variations of various signals within the embodiment of FIG. 3;
"FIGS. 7A-7D show chronograms related to different values of UP and LOCK as illustrated in Table 2;
"FIG. 8 shoes an exemplary decision flowchart of an algorithm employed by a state machine according to an embodiment;
"FIG. 9 illustrates the creation of a delayed data signal that can be used as the data input of the re-clocking flip-flop according to an embodiment of the invention;
"FIG. 10 illustrates the use of three masking windows (UP, DO, and LOCK) according to an alternative embodiment of the invention; and
"FIG. 11 is a schematic block diagram of a local oscillator signal generation circuit according to another embodiment of the invention."
URL and more information on this patent application, see: TOURRET, Jean-Robert. Local Oscillator Signal Generation. Filed
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