The assignee for this patent application is
Reporters obtained the following quote from the background information supplied by the inventors: "Description of Related Art
"Simulators, debuggers and accelerators that can be implemented in hardware, software or a combination of both, are typically are used in verification of program code as well as verification of designs of processor integrated circuits (ICs) and other large-scale logic.
"In simulation using a multi-threaded simulator, the handling of memory accesses is complicated, as hardware mechanisms that are provided to avoid memory access conflicts are not actually present in the simulator, and thus the simulator must handle memory accesses made during the simulation in a synchronized manner, which reduces simulation throughput. Further, debug facilities such as breakpoints, watches and protection exceptions are often set for memory locations or memory ranges, requiring the simulator to perform those checks in the simulation environment.
"Therefore, it would be desirable to provide a mechanism for managing accesses to memory that improves simulation throughput while synchronizing accesses and providing breakpoint, watch and protection capability for the simulator."
In addition to obtaining background information on this patent application, VerticalNews editors also obtained the inventors' summary information for this patent application: "The invention is embodied in a computer-performed simulation method, computer system and computer program product that simulates accesses to memory. The computer system is a computer system executing program instructions for carrying out the method, and the computer program product is a program for carrying out the method.
"The simulation method manages accesses to a frame of memory by using proxy frames to receive accesses to memory frames of a memory subsystem. Check frames can be inserted between the proxy frame and the memory frames, which if present, pre-process the accesses to the memory frames. If a check frame is not present for the accessed frame, the memory frame handles the request received from the proxy frame. The check frames can track write accesses to memory so that dirty frames can be tracked. The check frame may be a synchronization frame that stalls accesses from other simulator threads in a multi-threaded simulation environment. Other check frames may be chained between the proxy object and the memory frame to handle memory synchronization, breakpoints, memory watches, protections or for tracking accesses to the memory for other applications.
"The foregoing and other objectives, features, and advantages of the invention will be apparent from the following, more particular, description of the preferred embodiment of the invention, as illustrated in the accompanying drawings.
BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWING
"The novel features believed characteristic of the invention are set forth in the appended claims. The invention itself, however, as well as a preferred mode of use, further objectives, and advantages thereof, will best be understood by reference to the following detailed description of the invention when read in conjunction with the accompanying Figures, wherein like reference numerals indicate like components, and:
"FIG. 1 is a pictorial diagram depicting a simulation architecture in which the techniques disclosed herein can be practiced in accordance with embodiments of the invention.
"FIG. 2A and FIG. 2B are pictorial diagrams of simulated or actual memory access paths in the simulation architecture of FIG. 1A or the computer architecture of FIG. 1B.
"FIG. 3 is a pictorial diagram depicting on example of check frame 16A of FIG. 2B.
"FIGS. 4A-4C are pictorial diagrams depicting a sequence of steps in a method of synchronization in accordance with an embodiment of the present invention.
"FIGS. 5A-5C are pictorial diagrams depicting a sequence of steps in a method of synchronization in accordance with another embodiment of the present invention.
"FIG. 6 is a flowchart depicting a method of managing memory access in accordance with an embodiment of the present invention.
"FIG. 7 is a block diagram illustrating a computer system in which program code according to an embodiment of the present invention implementing a method according to an embodiment of the invention is executed."
For more information, see this patent application: Bashore,
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