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Researchers Submit Patent Application, "Structure and Method for In-Line Defect Non-Contact Tests", for Approval

June 25, 2014



By a News Reporter-Staff News Editor at Electronics Newsweekly -- From Washington, D.C., VerticalNews journalists report that a patent application by the inventors Ding, Hanyi (Colchester, VT); Feng, Kai D. (Hopewell Junction, NY); Wang, Ping-Chuan (Hopewell Junction, NY); Yang, Zhijian (Stormville, NY), filed on December 5, 2012, was made available online on June 12, 2014.

The patent's assignee is International Business Machines Corporation.

News editors obtained the following quote from the background information supplied by the inventors: "The present invention relates generally to defect detection in semiconductor device manufacturing, and, more particularly, to a test structure for determining open and short circuits in semiconductor devices.

"For advanced integrated circuit process, the wiring line width can be tens of nanometers. As a result one issue during production is electrical opens in the wiring lines. Electrical opens occur due to defects such as hollow metal, stress voiding, missing patterns and other process errors. Additionally, electrical shorts occur due to defects such as metal debris or out-diffusion between wiring lines. It is critical to have methods and test structures on the wafer to test for these errors in the production process which allows the production team to detect when an error occurs prior to completing the manufacture of the entire wafer.

"As part of the process monitoring and inline test for product chips, specially designed structures are often placed in Kerf areas, which are between functional dies and will be cut out during the dicing process. Such test structures should facilitate maximizing the efficiency of detection for shorts and opens by allowing for as many tests as necessary, using a minimal amount of area, while still detecting all defects of concern with minimal 'escapes' (i.e. missed defects).

"Certain test structures for wiring line in existence, such as comb structures for example, are configured to detect short circuits. Other test structures may be a serpentine structure, hybrid serpentine structures made up of serpentine structures and comb structures to detect both short and open circuits, and finally spiral structures such as that found in U.S. Pat. No. 7,187,179, entitled, 'Wiring Test Structure for Determining Open and Short Circuits in Semiconductor Devices'.

"The current structures for open and short defect monitoring are designed for contact DC probing, where metal probes are brought in electrical contact with probe pads in order to detect open and short circuits. DC probing may subject the wafer to mechanical damage in low-k dielectrics and metal layer causing yield and reliability issues in advanced technologies. In addition metal probe pads (typically 60 um.times.80 um each) take significant space in the kerf area."

As a supplement to the background information on this patent application, VerticalNews correspondents also obtained the inventors' summary information for this patent application: "According to one embodiment of the present invention, a method comprises the steps of forming a spiral test structure on a wafer, the spiral test structure has a capacitor. A frequency signal is provided to the spiral test structure by a test apparatus, for example a sensing spiral. The test structure is monitored for a reflected resonant frequency from the spiral test structure. By monitoring the output it is possible to determine if an open or a short is present in the spiral test structure. This is possible as the test structure will resonate in view of the spiral contacted at either end by a capacitor. When the spiral test structure does not have opens or shorts, it will resonate at a first frequency, when an open or a short is present the resonate frequency will change. The frequency applied by the sensing spiral may be a range of frequencies for example the range comprising 1 GHz to 5 GHz, or the frequency range may be larger for example from 100 KHz to 10 GHz.

"The method may further comprise the step when an open or a short is detected determining if the errors are acceptable, in the case errors are acceptable testing additional spiral test structures. If the errors are not acceptable determining if the wafer can be reworked.

"A system may be utilized to implement the method, where the system may comprise a wafer having a plurality of spiral test structures located on the kerf of the wafer. The spiral structures may be located on a first metal layer or on multiple metal layers. The system may further incorporate a test apparatus having a frequency transmitter and a receiver. The test apparatus may be a sensing spiral which may be placed over the spiral test structures. A controller may provide a range of frequencies to the test apparatus and receiving the resonant frequencies from the test apparatus. The resonant frequencies will be seen as reductions in signal response at the test apparatus. The range of frequencies may be for example from one to five GHz.

"The spiral test structure may comprise a spiral winding on a metal layer of a wafer with a capacitor connected to either end of said spiral winding. This will allow for the spiral test structure to resonate when a frequency signal is presented to apparatus. The resonant frequency of the spiral test structure may changes when a short or an open is present. The spiral test structure may be located on the kerf of the wafer. Further the capacitor may be for example a front end of line capacitor or a back end of line capacitor.

"A second embodiment may comprise the steps of forming a spiral test structure on a wafer, the spiral test structure having a capacitor. A frequency signal may be provided to the spiral test structure from a test apparatus. When a signal is provided to the spiral test structure the output is monitored to identify a reflected resonant frequency from the spiral test structure. Finally based on the detected resonant frequency it is possible to determine if a short or an open is present in the spiral test structure.

"The test apparatus may comprise a sensing spiral, wherein the sensing spiral is placed over the spiral test structure. Further the frequency signal may be a range of frequencies for example from 1 GHz to 5 GHz or an even greater range for example from 100 KHz to 10 GHz. When a short or an open is detected it is possible to determine if the errors are acceptable, in the case errors are acceptable testing additional spiral test structures. In the event the errors are not acceptable determining if the wafer can be reworked.

"In a further embodiment, it is possible to test for both shorts and opens and test for these errors on multiple layers. For example by incorporating test structures with smaller wire widths and larger spacing it is possible to test for opens, while simultaneously, by placing structures with larger wire widths and smaller spacing it is possible to test for shorts. In addition by designing the spiral test structures to have different resonant frequencies it is possible to test multiple test structures simultaneously.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS

"FIG. 1 illustrates a test spiral structure which is built into the kerf of the wafer.

"FIG. 2 illustrates a one embodiment of the invention incorporating a FEOL capacitor.

"FIG. 3 illustrates a second embodiment of the invention incorporating a BEOL capacitor.

"FIG. 4 illustrates a sensing spiral.

"FIG. 5 illustrates a system incorporating a sensing spiral and a test structure, with a controller connected to the sensing spiral.

"FIG. 6A illustrates a graph of a simulation of test results for opens for a sensing spiral placed 30 um above a test structure.

"FIG. 6B illustrates a graph of a simulation of test results for opens for a sensing spiral placed 50 um above a test structure.

"FIG. 6C illustrates a graph of a simulation of test results for a short for a sensing spiral placed 30 um above a test structure.

"FIG. 7 illustrates an embodiment in which multiple test structures may be embedded in the kerf around a device.

"FIG. 8 is a method for testing a wafer utilizing an embedded test spiral."

For additional information on this patent application, see: Ding, Hanyi; Feng, Kai D.; Wang, Ping-Chuan; Yang, Zhijian. Structure and Method for In-Line Defect Non-Contact Tests. Filed December 5, 2012 and posted June 12, 2014. Patent URL: http://appft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&u=%2Fnetahtml%2FPTO%2Fsearch-adv.html&r=5135&p=103&f=G&l=50&d=PG01&S1=20140605.PD.&OS=PD/20140605&RS=PD/20140605

Keywords for this news article include: Electronics, Semiconductor, International Business Machines Corporation.

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Source: Electronics Newsweekly


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