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Researchers Submit Patent Application, "Semiconductor Memory Device and Method of Manufacturing the Same", for Approval

June 25, 2014



By a News Reporter-Staff News Editor at Electronics Newsweekly -- From Washington, D.C., VerticalNews journalists report that a patent application by the inventors CHO, Jung Il (Icheon-si Gyeonggi-do, KR); CHOI, Jong Moo (Cheongju-si Chungcheongbuk-do, KR); JUNG, Eun Joo (Icheon-si Gyeonggi-do, KR), filed on February 28, 2013, was made available online on June 12, 2014.

The patent's assignee is Sk Hynix Inc.

News editors obtained the following quote from the background information supplied by the inventors: "Various embodiments relate generally to a semiconductor memory device and a method of manufacturing the same and, more particularly, to a semiconductor memory device including an air gap and a method of manufacturing the same.

"A semiconductor memory device includes a plurality of memory cells configured to store data and devices configured to perform various operations. High-density integration techniques have become increasingly important to achieve higher data capacity and reduced weight for a semiconductor memory device. In particular, since memory cells occupy a large space of the semiconductor chip, a reduction in size of the memory cells and a reduction in space between adjacent memory cells have become issues.

"Among semiconductor memory devices, a NAND flash memory device includes memory cells arranged in units of strings. Isolation layers, formed of insulating materials, are filled between these strings, that is, at isolation regions. The isolation layers function to block electrical influence between adjacent strings and memory cells, e.g., interference therebetween.

"However, with increasing integration degree of the semiconductor memory device, the isolation layers formed of the insulating materials may have limitations in blocking interference between the memory cells arranged in the strings and the memory cells, which may deteriorate the reliability of the semiconductor memory device."

As a supplement to the background information on this patent application, VerticalNews correspondents also obtained the inventors' summary information for this patent application: "Various embodiments relate to a semiconductor memory device, preventing interference between semiconductor memory devices, and a method of manufacturing the same.

"A semiconductor memory device according to an embodiment of the present invention includes a semiconductor substrate in which an active region and an isolation region are defined, a tunnel insulating layer and a floating gate formed on the semiconductor substrate in the active region, a trench formed in the semiconductor substrate in the isolation region, a dielectric layer formed along a top surface and a portion of a side surface of the floating gate, wherein the dielectric layer extends higher than a surface of the semiconductor substrate in the isolation region and defines an air gap in the trench, and a control gate formed on the dielectric layer, wherein the dielectric layer includes the first nitride layer, a first oxide layer, a second nitride layer and a second oxide layer.

"A method of manufacturing a semiconductor memory device according to an embodiment of the present invention includes forming a tunnel insulating layer and a first conductive layer configured as a floating gate in an active region of a semiconductor substrate, and forming a trench in an isolation region of the semiconductor substrate, filling the trench with a sacrificial layer having a top surface higher than a surface of the semiconductor substrate, forming a first oxide layer along an entire surface of a resultant structure filled with the sacrificial layer, forming an air gap in the isolation region by removing the sacrificial layer while maintaining the first oxide layer, transforming a portion of the first oxide layer into a first nitride layer, forming a second nitride layer and a second oxide layer over the first oxide layer, and forming a second conductive layer configured as a control gate on the second oxide layer.

BRIEF DESCRIPTION OF THE DRAWINGS

"FIGS. 1A to 1H are cross-sectional views illustrating a method of manufacturing a semiconductor memory device according to an embodiment of the present invention;

"FIGS. 2A to 2K are cross-sectional views illustrating a method of manufacturing a semiconductor memory device according to an embodiment of the present invention; and

"FIG. 3 is a view illustrating a principle of removing a sacrificial layer."

For additional information on this patent application, see: CHO, Jung Il; CHOI, Jong Moo; JUNG, Eun Joo. Semiconductor Memory Device and Method of Manufacturing the Same. Filed February 28, 2013 and posted June 12, 2014. Patent URL: http://appft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&u=%2Fnetahtml%2FPTO%2Fsearch-adv.html&r=5693&p=114&f=G&l=50&d=PG01&S1=20140605.PD.&OS=PD/20140605&RS=PD/20140605

Keywords for this news article include: Electronics, Sk Hynix Inc, Semiconductor.

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Source: Electronics Newsweekly


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