The patent's assignee is
News editors obtained the following quote from the background information supplied by the inventors: "With development of semiconductor technology, feature size of Metal Oxide Semiconductor Field Effect Transistors (MOSFETs) decreases continuously. The reduced size of the MOSFET may cause a current leakage problem. Physical thickness of a gate dielectric layer can be increased without changing Equivalent Oxide Thickness (EOT) by use of a high-K gate dielectric layer, so as to reduce tunneling leakage current. However, a conventional poly-silicon gate is incompatible with the high-K gate dielectric layer. Depletion effect of the polysilicon gate can be avoided by using a metal gate together with the high-K gate dielectric layer. Meanwhile, gate resistance can be reduced and boron penetration can be avoided, thereby increasing reliability of the device. Consequently, combination of the metal gate and the high-K gate dielectric layer is widely used in the MOSFET. However, the combination of the metal gate and the high-K gate dielectric layer still faces various challenges, such as thermal stability problem and interface state problem. In particular, it is difficult for the MOSFET comprising the metal gate and the high-K gate dielectric layer to achieve a properly low threshold voltage due to Fermi pinning effect.
"In order to achieve a proper threshold voltage, an N-type MOSFET should have an effective work function near the bottom of conductive band of Si (about 4.1 eV). For the N-type MOSFET, a desired threshold voltage can be achieved by selecting a proper combination of the metal gate and the high-K gate dielectric layer. However, it is difficult to achieve such a low effective work function merely by selection of materials."
As a supplement to the background information on this patent application, VerticalNews correspondents also obtained the inventors' summary information for this patent application: "The present disclosure provides an improved method for manufacturing an N-type MOSFET, in which an effective work function of a semiconductor device can be adjusted during manufacturing process.
"According to the present disclosure, there is provided a method for manufacturing an N-type MOSFET, comprising: forming a part of the MOSFET on a semiconductor substrate, the part of the MOSFET comprising source/drain regions in the semiconductor substrate, a replacement gate stack between the source/drain regions above the semiconductor substrate, and a gate spacer surrounding the replacement gate stack; removing the replacement gate stack of the MOSFET to form a gate opening exposing a surface of the semiconductor substrate; forming an interface oxide layer on the exposed surface of the semiconductor; forming a high-K gate dielectric layer on the interface oxide layer in the gate opening; forming a first metal gate layer on the high-K gate dielectric layer; implanting dopant ions into the first metal gate layer; forming a second metal gate layer on the first metal gate layer to fill the gate opening; and performing annealing to cause the dopant ions to diffuse and accumulate at an upper interface between the high-K gate dielectric layer and the first metal gate layer and a lower interface between the high-K gate dielectric layer and the interface oxide layer, and also to generate electric dipoles by interfacial reaction at the lower interface between the high-K gate dielectric layer and the interface oxide layer.
"According to the method, characteristics of the metal gate may be altered by the dopant ions accumulated at the upper interface of the high-K gate dielectric layer so that the effective work function of the MOSFET can be adjusted to advantage. On the other hand, electric dipoles having suitable polarities may be formed by interfacial reaction of the dopant ions accumulated at the lower interface of the high-K gate dielectric layer, so that the effective work function of the MOSFET can be further adjusted to advantage. Semiconductor devices manufactured by the method may have good stability and excellent performance in adjusting the effective work function of the metal gate.
BRIEF DESCRIPTION OF THE DRAWINGS
"The present disclosure will be described in detail with reference to the drawings to enable better understanding of the present disclosure, in which:
"FIGS. 1-6 schematically show sectional views of semiconductor structures at respective phases of manufacturing an N-type MOSFET according to an embodiment of a method of the present disclosure."
For additional information on this patent application, see: Xu, Qiuxia; Zhu, Huilong; Zhou, Huajie; Xu, Gaobo. Method for Manufacturing N-Type Mosfet. Filed
Keywords for this news article include: Semiconductor,
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