News Column

Researchers Submit Patent Application, "Loopback Structure and Data Loopback Processing Method of Processor", for Approval

June 24, 2014



By a News Reporter-Staff News Editor at Information Technology Newsweekly -- From Washington, D.C., VerticalNews journalists report that a patent application by the inventors Li, Lihuang (Shenzhen, CN); Li, Wei (Shenzhen, CN), filed on September 15, 2011, was made available online on June 12, 2014.

The patent's assignee is Zte Corporation.

News editors obtained the following quote from the background information supplied by the inventors: "A processor is a core component in a chip, and efficiency and power consumption of the processor affect largely that of the whole chip. Therefore, what needs to be considered in processor-architecture design is how to increase the efficiency of the processor and decrease the power consumption of the processor.

"As shown in FIG. 1, three data channels are provided in conventional processor-architecture, namely:

"a 1st channel through ' memory.fwdarw.data reading unit.fwdarw.register file unit ';

"a 2nd channel through 'register file unit.fwdarw.computing unit.fwdarw.register file unit ', which is also called a front channel; and

"a 3rd channel through 'register file unit.fwdarw.data storing unit.fwdarw.memory '.

"In the conventional processor-architecture, before starting a computation, the data reading unit first reads an operand in the memory and sends the operand to the register file unit; then the computing unit reads the operand from the register file unit to start the computation, and writes a result of the computation back into the register file unit; finally, the data storing unit reads the result of the computation from the register file unit, and stores the result of the computation in the memory.

"In the conventional processor-architecture, although data computation may be performed in cycles within the front channel consisting of 'register file unit.fwdarw.computing unit.fwdarw.register file unit', the computing unit however can perform only an arithmetic logic computation, but not a special data transformation provided by the data reading unit and the data storing unit (such as data rotation-displacement). Therefore, if a special data transformation provided by the data reading unit and the data storing unit is to be performed, the processor has to write data back into the memory, and then read the data from the memory once again. An operation directed to the memory will cost the power consumption and time of the processor, in which case frequent reading-writing of the memory by the processor will have a major impact on the efficiency and power consumption of the whole processor."

As a supplement to the background information on this patent application, VerticalNews correspondents also obtained the inventors' summary information for this patent application: "In view of this, a main purpose of the disclosure is to provide a loopback structure and data loopback processing method of a processor, so as to increase efficiency of the processor and decrease power consumption of the processor.

"To achieve this purpose, a technical solution of the disclosure is implemented as follows.

"The disclosure provides a loopback structure of a processor, which includes a register file unit, a data storing unit, and a data reading unit: wherein:

"the register file unit is configured to provide a data reading-writing service for the data storing unit and the data reading unit;

"the data storing unit is connected to the register file unit, and is configured to read data via a reading port of the register file unit, to perform a data transformation on the read data, and to feed the transformed data back to the data reading unit; and

"the data reading unit is connected to the register file unit and the data storing unit, and is configured to transform the data fed back by the data storing unit, and to write the transformed data in the register file unit via a writing port of the register file unit.

"A data computing and transforming unit may be connected between the data storing unit and the data reading unit, and

"the data computing and transforming unit may be configured to perform computation and transformation processing on the data fed back by the data storing unit, and provide the processed data to the data reading unit.

"The data storing unit may be configured to mask an operation directed to a memory of the processor by the data storing unit itself when the data storing unit processes the data read via the reading port.

"The loopback structure may further include a computing unit connected to the register file unit and configured to read a source operand from the register file unit, to perform a data computation based on the source operand, and to write a result of the computation in the register file unit.

"The data storing unit may be configured to read the result of the computation based on the source operand via the reading port of the register file unit, to perform the data transformation on the read result of the computation, and to feed the transformed result of the computation back to the data reading unit; and

"accordingly, the data reading unit may be configured to transform the result of the computation fed back by the data storing unit, and to write the transformed result of the computation in the register file unit via the writing port of the register file unit.

"The data transformation may be a data rotation-displacement operation.

"The disclosure further provides a data loopback processing method of a processor, including:

"reading, by a data storing unit, data via a reading port of a register file unit, performing a data transformation on the read data, and feeding the transformed data back to a data reading unit; and

"transforming, by the data reading unit, the data fed back by the data storing unit, and writing the transformed data in the register file unit via a writing port of the register file unit.

"The method may further include:

"performing, by a data computing and transforming unit connected between the data storing unit and the data reading unit, performing computation and transformation processing on the data fed back by the data storing unit, and providing the processed data to the data reading unit.

"The method may further include:

"masking, by the data storing unit, an operation directed to a memory of the processor by the data storing unit itself when the data storing unit processes the data read via the reading port.

"The method may further include:

"reading, by a computing unit connected to the register file unit, a source operand from the register file unit, performing a data computation based on the source operand, and writing a result of the computation in the register file unit.

"The method may further include:

"reading, by the data storing unit, the result of the computation based on the source operand via the reading port of the register file unit, performing the data transformation on the read result of the computation, and feeding the transformed result of the computation back to the data reading unit; and

"transforming, by the data reading unit, the result of the computation fed back by the data storing unit, and writing the transformed result of the computation in the register file unit via the writing port of the register file unit.

"The data transformation may be a data rotation-displacement operation.

"The loopback structure and data loopback processing method of a processor provided by the disclosure provides an instruction and a channel directly from the data storing unit to the data reading unit; by providing the instruction and channel, after the computation by the computing unit and the data transformation by the data storing unit, data are not written into the memory directly, but are looped and fed back to the data reading unit. The channel reuses a special data transformation function of the data storing unit and the data reading unit (including data rotation-displacement and the like) as well as their reading and writing ports of the register file unit, and another data computing and transforming unit may be added between the data storing unit and the data reading unit as needed; this channel and the channel of 'register file unit.fwdarw.computing unit.fwdarw.register file unit ' are independent of each other, and may operate in parallel, that is, they may work independently without affecting each other.

"With the disclosure, reading and writing operations to the memory by the processor, or any reading and writing conflicts due to such operations, is exempted, thereby increasing work efficiency of the processor and decreasing power consumption of the processor effectively.

BRIEF DESCRIPTION OF THE DRAWINGS

"FIG. 1 is a schematic diagram of processor-architecture in the related art;

"FIG. 2 is a 1st schematic diagram of a loopback structure of a processor in an embodiment of the disclosure;

"FIG. 3 is a 2nd schematic diagram of a loopback structure of a processor in an embodiment of the disclosure;

"FIG. 4 is a sequence diagram of data loopback processing by a processor in an embodiment of the disclosure;

"FIG. 5 is a schematic diagram of independent front and the back channels in a loopback structure of a processor according to an embodiment of the disclosure; and

"FIG. 6 is a schematic diagram of a closed loop formed by a front channel and a back channel in a loopback structure of a processor according to an embodiment of the disclosure."

For additional information on this patent application, see: Li, Lihuang; Li, Wei. Loopback Structure and Data Loopback Processing Method of Processor. Filed September 15, 2011 and posted June 12, 2014. Patent URL: http://appft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&u=%2Fnetahtml%2FPTO%2Fsearch-adv.html&r=787&p=16&f=G&l=50&d=PG01&S1=20140605.PD.&OS=PD/20140605&RS=PD/20140605

Keywords for this news article include: Zte Corporation, Information Technology, Information and Data Transformation.

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Source: Information Technology Newsweekly


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