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Researchers Submit Patent Application, "Circuit to Control the Effect of Dielectric Absorption in Dynamic Voltage Scaling Low Dropout Regulator", for...

June 25, 2014



Researchers Submit Patent Application, "Circuit to Control the Effect of Dielectric Absorption in Dynamic Voltage Scaling Low Dropout Regulator", for Approval

By a News Reporter-Staff News Editor at Electronics Newsweekly -- From Washington, D.C., VerticalNews journalists report that a patent application by the inventor Howes, Rupert (Stroud, GB), filed on December 3, 2012, was made available online on June 12, 2014.

The patent's assignee is Dialog Semiconductor Gmbh.

News editors obtained the following quote from the background information supplied by the inventors: "Battery powered applications such as smart-phones and tablet computers demand long battery life and therefore highly power efficient circuits. Often, the power supply voltage of digital circuits for the battery power applications must be adjusted during operation to minimize power consumption, since the power dissipated is proportional to the square of the power supply voltage. To achieve the required speed of operation, a certain minimum supply voltage is required. As demand fluctuates, the supply voltage is adjusted as required.

"The power supply for these types of circuits is often regulated down from the main battery by a voltage regulator, e.g. buck converter or linear regulator.

"Buck voltage converters are generally power efficient but can consume a significant area and need bulky external components (inductors). These circuits are often used for higher load currents where the area of the control circuit is not significant compared with the size of the power switches.

"However, for applications that require only a modest load current, the area penalty of a buck converter may be unacceptable. In such cases, the use of a low dropout voltage regulator (LDO) can be more area efficient although with some loss of energy efficiency.

"A low dropout regulator is a class of linear regulator that is designed to minimize the saturation of the output pass transistor and its drive requirements. A low-dropout linear regulator will operate with input voltages only slightly higher than the desired output voltage. FIG. 1 is a schematic of a low dropout voltage regulator of the prior art. The main components of a low dropout voltage regulator are a power field effect transistor M.sub.out having a source and bulk connected to a battery BAT to receive a battery voltage V.sub.bat. The gate of the power field effect transistor M.sub.out is connected to an output of a differential error amplifier Op1. One input of the differential error amplifier Op1 monitors the fraction of the output determined by the resistor ratio of R1 and R2. The second input to the differential error amplifier Op1 is from a stable voltage reference (bandgap reference) V.sub.Ref. If the output voltage rises too high relative to the reference voltage V.sub.Ref, the drive to the power field effect transistor M.sub.out changes to maintain a constant output voltage V.sub.out developed across the load capacitance C.sub.Load.

"Dielectric absorption, also called dielectric relaxation or capacitor soaking, is the tendency of a capacitor to recharge itself after being discharged. Dielectric absorption is also the dominant loss mechanism of the entire usable range of most capacitors that affect the performance of error amplifiers, digital-to-analog converters, other sample and hold circuitry, and switched capacitor circuitry. The load capacitance C.sub.Load of the low dropout regulator is a discrete capacitor that is subject to the dielectric absorption phenomena and will impact the functioning of the differential error amplifier Op1 to cause loss of regulation of the low dropout regulator."

As a supplement to the background information on this patent application, VerticalNews correspondents also obtained the inventor's summary information for this patent application: "An object of this disclosure is to provide is to provide a circuit and method for compensating for dielectric absorption current of a load capacitor of a low dropout voltage regulator.

"To accomplish at least this object, a dielectric absorption current compensation circuit generates a profile current that is applied to an output of the low dropout voltage regulator and in parallel with the load capacitor to compensate for the dielectric absorption current from recharging the load capacitor. In some embodiments, the dielectric absorption current compensation circuit is an analog dielectric absorption current compensation circuit providing an analog profile compensation current mirroring the dielectric absorption current. In other embodiments, digital dielectric absorption current compensation circuit providing a digital profile compensation current having discrete levels approximately mirroring the dielectric absorption current.

"The analog dielectric absorption current compensation circuit has a programmable profile current generator that generates the profile current. A switchable current mirror transfers a mirror profile current to the load capacitor to compensate for the dielectric absorption current. The switchable current mirror has a first switch with a first terminal connected to an output of the programmable current source and a second terminal connected to a drain and gate of a diode-connected transistor. A source of the diode-connected transistor is connected to a ground reference voltage source. A ballast timing capacitor has a first plate connected to the drain and gate of the diode-connected transistor and a second plate connected to the ground reference voltage source to control the profile of the compensating current within the dielectric absorption compensation circuit.

"A second switch has a first terminal connected to the drain and gate of the diode-connected transistor and second terminal connected to a gate of a second transistor. The drain of the second transistor is connected to an output of the low dropout regulator and in parallel with the output capacitor of the low dropout regulator. A source of the second transistor is connected to the ground reference voltage source. A third switch has a first terminal connected to the gate of the second transistor and the second terminal of the second switch and a second terminal connected to the ground reference voltage source.

"When the low dropout regulator is in a steady state condition, the first switch is activated to close the connection from the profile current source to the diode-connected transistor. The second switch is deactivated to disconnect the gate of the second transistor from the drain and gate of the diode-connected transistor. The third switch is activated to connect the gate of the second transistor to the ground reference voltage source.

"When the output of the low dropout regulator is programmed to lower voltage level, the output voltage level is brought to the lower voltage level. At this time, the voltage across the output capacitor of the low dropout voltage regulator will begin to recharge and the output voltage will begin to rise. At this time the first switch and the third switch will deactivate and second switch will activate. The analog profile compensation current source will source current with a magnitude that matches the current generated as the output capacitor recharges. The switchable current mirror will provide the mirrored profile current to the output of the low dropout regulator to counteract the current generated by the recharging of the output capacitor.

"The digital dielectric absorption current compensation circuit includes a digital-to-analog circuit that receive multiple data bits and generates the digital profile compensation current based on a data state of the data bits. The digital profile compensation current level is generated as the sum of the current levels based on a data state of applied to the data bits. The digital-to-analog circuit has multiple switching transistors that are connected such that a gate of each of the switching transistors receives one of the data bits. The sources of the switching transistors are commonly connected to a ground reference voltage source. A first terminal of each of multiple current determining resistors is connected to a drain of each of the plurality of switching transistors. The second terminals of the current determining resistors are commonly connected to the output of the low dropout voltage regulator for transferring the digital profile compensation current to the load capacitor to compensate for the dielectric absorption current.

"When all of the data bits are at a first data state all of the plurality of switching transistors are turned on and the digital profile compensation current is a maximum current level. When all of the data bits are at a second data state all of the plurality of switching transistors are turned off and the digital profile compensation current is a zero current level. When any of the data bits are at a first data state those of the plurality of switching transistors with gates at the first data state are turned on, those of the switching transistors with gates at the second data state are turned off, and the digital profile compensation current is a current level equal to the sum of the current through each of those of the plurality of switching transistors with gates at the first data state and turned on. The digital profile compensation current is formed by selectively setting the data bits to the first data state to approximate the dielectric absorption current.

"In some embodiments, at least this object is accomplished by a low dropout voltage regulator including a dielectric absorption current compensation circuit that generates a profile current that is applied to an output of the low dropout voltage regulator and in parallel with the output load capacitor of the low dropout voltage regulator to compensate for the dielectric absorption current of the recharging of the output load capacitor. In some embodiments, the dielectric absorption current compensation circuit is an analog dielectric absorption current compensation circuit providing an analog profile compensation current mirroring the dielectric absorption current. In other embodiments, digital dielectric absorption current compensation circuit providing a digital profile compensation current having discrete levels approximately mirroring the dielectric absorption current.

"The analog dielectric absorption current compensation circuit has a profile current generator connected to a switchable current mirror circuit to provide a profile current that mirrors the dielectric absorption recharging current of the output load capacitor of the low dropout regulator. The switchable current generator is deactivated when the low dropout voltage regulator is in a steady state condition (output voltage not changing). It is activated after the low dropout voltage regulator has been programmed to a lower voltage and the output voltage has been reduced. After the output voltage has been reduced, the output load capacitor begins to recharge and the voltage across the output load capacitor begins to rise. To compensate for the recharging voltage, the switchable current source is activated and a mirrored version of the profile current is applied to the output of the low dropout voltage regulator to compensate for the dielectric absorption current of the recharging output load capacitor.

"The analog dielectric absorption current compensation circuit has a programmable current source that alters the voltage and therefore the charge stored on a ballast timing capacitor. During normal operation, a first switch is activated to connect the programmable current source to the ballast timing capacitor for charging the ballast timing capacitor to a voltage limited by a diode-connected transistor with the switchable current source. A second switch within the switchable current source is deactivated and a third switch within switchable current source is activated to connect the gate of a second transistor of the switchable current source to the ground reference voltage level to turn off the second transistor. The amount of charge and the voltage level stored on the ballast timing capacitor determines the magnitude of the analog profile compensation current. The higher the voltage level present on the ballast timing capacitor, the greater the analog profile compensation current.

"When the analog dielectric absorption current compensation circuit is activated, the first and the third switches are opened and the second switch is closed. The analog compensation current in the second transistor is activated to a current level that is approximately equivalent to the level of the dielectric absorption current caused during the recharging of the output capacitor due to the dielectric absorption. The diode-connected transistor and the second transistor function as a current mirror to provide the analog compensation current to maintain the output voltage level at the output terminal of the low dropout voltage regulator at the disabled voltage level. The ballast timing capacitor is used to control the timing profile for the analog compensation current flowing through the second transistor. When the analog dielectric absorption compensation circuit is activated, the ballast timing capacitor is gradually discharged through the diode-connected transistor. Since the analog compensation current decays over time due to the discharge of ballast timing capacitor through diode-connected transistor, a higher analog compensation current also corresponds to a greater total amount of compensation charge removed from the external capacitor because it takes longer for ballast timing capacitor to be fully discharged.

"The digital dielectric absorption current compensation circuit includes a digital-to-analog circuit that receive multiple data bits and generates the digital profile compensation current based on a data state of the data bits. The digital profile compensation current level is generated as the sum of the current levels based on a data state of applied to the data bits. The digital-to-analog circuit has multiple switching transistors that are connected such that a gate of each of the switching transistors receives one of the data bits. The sources of the switching transistors are commonly connected to a ground reference voltage source. A first terminal of each of multiple current determining resistors is connected to a drain of each of the plurality of switching transistors. The second terminals of the current determining resistors are commonly connected to the output of the low dropout voltage regulator for transferring the digital profile compensation current to the load capacitor to compensate for the dielectric absorption current.

"When all of the data bits are at a first data state, all of the switching transistors are turned on and the digital profile compensation current is a maximum current level. When all of the data bits are at a second data state all of the plurality of switching transistors are turned off and the digital profile compensation current is a zero current level. When any of the data bits are at a first data state those of the plurality of switching transistors with gates at the first data state are turned on, those of the switching transistors with gates at the second data state are turned off, and the digital profile compensation current is a current level equal to the sum of the current through each of those of the plurality of switching transistors with gates at the first data state and turned on. The digital profile compensation current is formed by selectively setting the data bits to the first data state to approximate the dielectric absorption current.

"In some embodiments, at least this object is accomplished by an apparatus performing a method for compensating for the dielectric absorption current from the recharging of the output load capacitor of a low dropout voltage regulator. The low dropout voltage regulator is requested to decrease its output voltage. An internal load current source is enabled to decrease the output voltage of the low dropout voltage regulator by adjusting the charge of the output load capacitor. The output voltage of the low dropout voltage regulator is ramped down until it brought to a lower voltage level and the internal load voltage source is disabled. A profile current is applied after the low dropout voltage regulator is disabled to counteract the dielectric absorption current of the recharging output load capacitor to prevent the low dropout voltage regulator from becoming unregulated.

BRIEF DESCRIPTION OF THE DRAWINGS

"FIG. 1 is a schematic of a low dropout voltage regulator of the prior art.

"FIG. 2 is a schematic diagram of Howes, et al. of a battery driven power supply including a low dropout voltage regulator with dynamic voltage control.

"FIG. 3 is a plot of the timing of the output voltage level of the low dropout voltage regulator and the current of the dynamic voltage control current source of Howes, et al.

"FIG. 4 is a plot of the output voltage response of the low dropout voltage regulator after dynamic voltage control current source ramp down with transient load current applied showing excessive transient load response of Howes, et al.

"FIG. 5 is a schematic diagram of an error amplifier of the low dropout voltage regulator of FIG. 2.

"FIG. 6 is a schematic of an embodiment of a low dropout voltage regulator with dynamic voltage control including a dielectric absorption current compensation circuit of this disclosure.

"FIG. 7 is plot of the timing of the low dropout voltage regulator with dynamic voltage control including a dielectric absorption current compensation circuit of this disclosure.

"FIG. 8 is a schematic of the dielectric absorption current compensation circuit for implementing continuous time compensation for the capacitor dielectric absorption relaxation current of this disclosure.

"FIG. 9 is a plot comparing the continuous time profile current and dielectric absorption relaxation current of the capacitor dielectric absorption compensation circuit of the present disclosure.

"FIG. 10 is a schematic of the dielectric absorption current compensation circuit for implementing digital compensation for the capacitor dielectric absorption relaxation current of this disclosure.

"FIG. 11 is a plot comparing the digital profile compensation current and dielectric absorption relaxation current of the capacitor dielectric absorption compensation circuit of the present disclosure.

"FIG. 12 is a flowchart for a method for operating a dynamic voltage controlled low dropout voltage regulator with a capacitor dielectric absorption compensation circuit of the present disclosure."

For additional information on this patent application, see: Howes, Rupert. Circuit to Control the Effect of Dielectric Absorption in Dynamic Voltage Scaling Low Dropout Regulator. Filed December 3, 2012 and posted June 12, 2014. Patent URL: http://appft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&u=%2Fnetahtml%2FPTO%2Fsearch-adv.html&r=5193&p=104&f=G&l=50&d=PG01&S1=20140605.PD.&OS=PD/20140605&RS=PD/20140605

Keywords for this news article include: Electronics, Digital To Analog, Dialog Semiconductor Gmbh.

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Source: Electronics Newsweekly


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