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"Programming Schemes for Multi-Level Analog Memory Cells" in Patent Application Approval Process

June 24, 2014



By a News Reporter-Staff News Editor at Information Technology Newsweekly -- A patent application by the inventors Shalvi, Ofir (Ra'anana, IL); Sommer, Naftali (Rishon-LeZion, IL); Sokolov, Dotan (Ra'anana, IL); Kasorla, Yoav (Kfar Netar, IL), filed on February 6, 2014, was made available online on June 12, 2014, according to news reporting originating from Washington, D.C., by VerticalNews correspondents.

This patent application is assigned to Apple Inc.

The following quote was obtained by the news editors from the background information supplied by the inventors: "Several types of memory devices, such as Flash memories, use arrays of analog memory cells for storing data. Each analog memory cell stores a quantity of an analog value, also referred to as a storage value, such as an electrical charge or voltage. The storage value represents the information stored in the cell. In Flash memories, for example, each analog memory cell holds a certain amount of electrical charge. The range of possible analog values is typically divided into regions, each region corresponding to one or more data bit values. Data is written to an analog memory cell by writing a nominal analog value that corresponds to the desired bit or bits.

"Some memory devices, which are commonly referred to as Single-Level Cell (SLC) devices, store a single bit of information in each memory cell, i.e., each memory cell can be programmed to assume two possible memory states. Higher-density devices, often referred to as Multi-Level Cell (MLC) devices, store two or more bits per memory cell, i.e., can be programmed to assume more than two possible memory states.

"Flash memory devices are described, for example, by Bez et al., in 'Introduction to Flash Memory,' Proceedings of the IEEE, volume 91, number 4, April, 2003, pages 489-502, which is incorporated herein by reference. Multi-level Flash cells and devices are described, for example, by Eitan et al., in 'Multilevel Flash Cells and their Trade-Offs,' Proceedings of the 1996 IEEE International Electron Devices Meeting (IEDM), New York, N.Y., pages 169-172, which is incorporated herein by reference. The paper compares several kinds of multilevel Flash cells, such as common ground, DINOR, AND, NOR and NAND cells.

"Eitan et al., describe another type of analog memory cell called Nitride Read Only Memory (NROM) in 'Can NROM, a 2-bit, Trapping Storage NVM Cell, Give a Real Challenge to Floating Gate Cells?' Proceedings of the 1999 International Conference on Solid State Devices and Materials (SSDM), Tokyo, Japan, Sep. 21-24, 1999, pages 522-524, which is incorporated herein by reference. NROM cells are also described by Maayan et al., in 'A 512 Mb NROM Flash Data Storage Memory with 8 MB/s Data Rate', Proceedings of the 2002 IEEE International Solid-State Circuits Conference (ISSCC 2002), San Francisco, Calif., Feb. 3-7, 2002, pages 100-101, which is incorporated herein by reference. Other exemplary types of analog memory cells are Floating Gate (FG) cells, Ferroelectric RAM (FRAM) cells, magnetic RAM (MRAM) cells, Charge Trap Flash (CTF) and phase change RAM (PRAM, also referred to as Phase Change Memory-PCM) cells. FRAM, MRAM and PRAM cells are described, for example, by Kim and Koh in 'Future Memory Technology including Emerging New Memories,' Proceedings of the 24.sup.th International Conference on Microelectronics (MIEL), Nis, Serbia and Montenegro, May 16-19, 2004, volume 1, pages 377-384, which is incorporated herein by reference.

"Analog memory cells are often programmed using an iterative programming process that is commonly known as Program and verify (P&V). In a typical P&V process, a sequence of programming pulses is applied to a group of memory cells. The level of the programming pulses increases incrementally from pulse to pulse. The analog values programmed in the cells are read ('verified') after each pulse, and the iterations continue until the desired levels are reached.

"Some programming processes vary the parameters of the P&V process during programming. For example, U.S. Pat. No. 7,002,843, whose disclosure is incorporated herein by reference, describes a non-volatile memory device that is programmed by first performing a coarse programming process and subsequently performing a fine programming process. The coarse/fine programming methodology is enhanced by using an efficient verification scheme that allows some non-volatile memory cells to be verified for the coarse programming process while other non-volatile memory cells are verified for the fine programming process.

"As another example, U.S. Pat. No. 7,054,193, whose disclosure is incorporated herein by reference, describes write operations that simultaneously program multiple memory cells on the same word line in a Multi Bit Per Cell (MBPC) Flash memory. The write operations employ word line voltage variation, programming pulse width variation and data-dependent bit line and/or source line biasing to achieve uniform programming accuracy across a range of target threshold voltages.

"U.S. Pat. No. 7,349,263, whose disclosure is incorporated herein by reference, describes nonvolatile memory devices, which support P&V operations that improve the threshold voltage distribution within programmed memory cells. The improvement is achieved by reducing a magnitude of the programming voltage steps and increasing a duration of the verify operations once at least one of the plurality of memory cells undergoing programming has been verified as a 'passed' memory cell."

In addition to the background information obtained for this patent application, VerticalNews journalists also obtained the inventors' summary information for this patent application: "An embodiment of the present invention provides a method for data storage, including:

"storing first data bits in a set of multi-bit analog memory cells at a first time by programming the memory cells to assume respective first programming levels;

"storing second data bits in the set of memory cells at a second time that is later than the first time by programming the memory cells to assume respective second programming levels that depend on the first programming levels and on the second data bits; and

"selecting a storage strategy responsively to a difference between the first and second times, wherein the storage strategy is applied to at least one group of the data bits, selected from among the first data bits and the second data bits.

"In some embodiments, selecting the storage strategy is performed at the first time following storage of the first data bits. In an embodiment, selecting the storage strategy includes drawing an inference with respect to the time difference based on a status of the memory cells following the storage of the first data bits. Drawing the inference may include detecting that the set of the memory cells is partially-programmed following the storage of the first data bits. In another embodiment, selecting the storage strategy is performed at the second time.

"In some embodiments, the method includes reading from the memory cells at least one set of the stored data bits, selected from among the first data bits and the second data bits, wherein the storage strategy is applied in reading the at least one set of data bits. In an embodiment, selecting the storage strategy includes determining read thresholds to be used in reading the at least one set of data bits. In another embodiment, selecting the storage strategy includes selecting a decoding process for reading the at least one set of data bits.

"In yet another embodiment, selecting the storage strategy includes modifying a programming parameter used in storing the at least one group of the data bits. In still another embodiment, storing the first and second data bits includes applying to the memory cells a sequence of programming pulses that incrementally increase by a step size, and selecting the storage strategy includes modifying the step size. In a disclosed embodiment, storing the first and second data bits includes encoding the at least one group of the data bits with an Error Correction Code (ECC), and selecting the storage strategy includes modifying a redundancy level of the ECC.

"In an embodiment, programming the memory cells to assume the first and second programming levels includes writing to the cells predefined storage values that correspond to the respective programming levels and are separated from one another by predefined separations, and selecting the storage strategy includes modifying a separation between at least two programming levels selected from among the first and second programming levels. In another embodiment, selecting the storage strategy includes measuring the difference between the first and second times and comparing the measured difference to a threshold.

"In yet another embodiment, storing the second data bits includes retrieving the stored first data bits from the memory cells, caching the retrieved first data bits in a buffer and computing the second programming levels based on the cached first data bits and the second data bits, and selecting the storage strategy includes correcting errors in the cached first data bits and re-writing the first data bits, after correction of the errors, to the buffer prior to computing the second programming levels.

"In some embodiments, storing the second data bits includes retrieving the stored first data bits from the memory cells, caching the retrieved first data bits in a buffer and computing the second programming levels based on the cached first data bits and the second data bits, and selecting the storage strategy includes:

"correcting errors in the cached first data bits to produce error-corrected bits;

"re-retrieving the first data bits from the memory cells after storage of the second data bits; and

"selecting the storage strategy responsively to a discrepancy between the error-corrected bits and the re-retrieved first data bits.

"In a disclosed embodiment, selecting the storage strategy includes:

"retrieving at least part of the stored first data bits from the memory cells using one or more read thresholds;

"processing the retrieved first data bits so as to modify the read thresholds;

"re-retrieving the first data bits from the memory cells using the modified read thresholds; and

"computing the second programming levels responsively to the second data bits and the re-retrieved first data bits.

"In an embodiment, processing the retrieved first data bits includes detecting errors in the retrieved first data bits and modifying the read thresholds responsively to the detected errors.

"There is additionally provided, in accordance with an embodiment of the present invention, a method for data storage, including:

"storing first data bits in a memory device, which includes a first set of multi-bit analog memory cells and a second set of digital memory cells, by programming the analog memory cells to assume respective first programming levels;

"caching the first data bits in the digital memory cells;

"accepting second data bits for storage in the first set of analog memory cells;

"processing the accepted second data bits and the cached first data bits so as to compute respective second programming levels for the analog memory cells; and

"storing the second data bits in the first set of analog memory cells by programming the analog memory cells to assume the respective second programming levels.

"In some embodiments, caching the first data bits includes evaluating a criterion with respect to the first data bits, and caching the first data bits only responsively to meeting the criterion.

"In an embodiment, when the first data bits are not cached in the digital memory cells, the method includes retrieving the first data bits from the analog memory cells, correcting errors in the retrieved first data bits to produce error-corrected bits, and computing the second programming levels responsively to the second data bits and the error-corrected bits. In a disclosed embodiment, correcting the errors includes detecting the errors by error detection circuitry in the memory device and correcting the errors by error correction circuitry external to the memory device responsively to detecting the errors.

"In another embodiment, storing the first data bits includes applying to the analog memory cells a first sequence of programming pulses that incrementally increase by a first step size, and storing the second data bits includes applying to the analog memory cells a second sequence of the programming pulses that incrementally increase by a second step size, smaller than the first step size.

"There is also provided, in accordance with an embodiment of the present invention, apparatus for data storage, including:

"programming circuitry, which is coupled to store first data bits in a set of multi-bit analog memory cells at a first time by programming the memory cells to assume respective first programming levels, and to store second data bits in the set of memory cells at a second time that is later than the first time by programming the memory cells to assume respective second programming levels that depend on the first programming levels and on the second data bits; and

"a processor, which is configured to select a storage strategy responsively to a difference between the first and second times, wherein the storage strategy is applied to at least one group of the data bits, selected from among the first data bits and the second data bits.

"There is further provided, in accordance with an embodiment of the present invention, a memory device, including:

"a first set of multi-bit analog memory cells;

"a second set of digital memory cells; and

"control circuitry, which is coupled to store first data bits in the first set of analog memory cells by programming the analog memory cells to assume respective first programming levels, to cache the first data bits in the digital memory cells, to accept second data bits for storage in the first set of analog memory cells, to process the accepted second data bits and the cached first data bits so as to compute respective second programming levels for the analog memory cells, and to store the second data bits in the first set of analog memory cells by programming the analog memory cells to assume the respective second programming levels.

"In some embodiments, the memory device includes a device package, and the analog memory cells, the digital memory cells and the control circuitry are packaged in the device package.

"There is additionally provided, in accordance with an embodiment of the present invention, apparatus for data storage, including:

"a memory including a set of multi-bit analog memory cells;

"programming circuitry, which is coupled to store first data bits in the set of multi-bit analog memory cells at a first time by programming the memory cells to assume respective first programming levels, and to store second data bits in the set of memory cells at a second time that is later than the first time by programming the memory cells to assume respective second programming levels that depend on the first programming levels and on the second data bits; and

"a processor, which is configured to select a storage strategy responsively to a difference between the first and second times, wherein the storage strategy is applied to at least one group of the data bits, selected from among the first data bits and the second data bits.

"The present invention will be more fully understood from the following detailed description of the embodiments thereof, taken together with the drawings in which:

BRIEF DESCRIPTION OF THE DRAWINGS

"FIG. 1 is a block diagram that schematically illustrates a memory system, in accordance with an embodiment of the present invention;

"FIG. 2 is a flow chart that schematically illustrates a method for storing data in an array of multi-level memory cells, in accordance with an embodiment of the present invention;

"FIG. 3 is a block diagram that schematically illustrates a memory system, in accordance with an alternative embodiment of the present invention;

"FIG. 4 is a graph showing threshold voltage distributions in a group of multi-level memory cells, in accordance with an embodiment of the present invention; and

"FIGS. 5 and 6 are flow charts that schematically illustrate methods for storing data in an array of multi-level memory cells, in accordance with embodiments of the present invention."

URL and more information on this patent application, see: Shalvi, Ofir; Sommer, Naftali; Sokolov, Dotan; Kasorla, Yoav. Programming Schemes for Multi-Level Analog Memory Cells. Filed February 6, 2014 and posted June 12, 2014. Patent URL: http://appft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&u=%2Fnetahtml%2FPTO%2Fsearch-adv.html&r=382&p=8&f=G&l=50&d=PG01&S1=20140605.PD.&OS=PD/20140605&RS=PD/20140605

Keywords for this news article include: Apple Inc., Information Technology, Information and Data Storage.

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