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Patent Issued for Variable Resistance Memory Devices Having Reduced Reset Current

June 25, 2014



By a News Reporter-Staff News Editor at Electronics Newsweekly -- According to news reporting originating from Alexandria, Virginia, by VerticalNews journalists, a patent by the inventors Jeong, Ji-Hyun (Seoul, KR); Oh, JaeHee (Seongnam-si, KR); Joo, Heung Jin (Suwon-si, KR); Eun, Sung-Ho (Seoul, KR), filed on April 6, 2011, was published online on June 10, 2014.

The assignee for this patent, patent number 8748884, is Samsung Electronics Co., Ltd. (Suwon-si, KR).

Reporters obtained the following quote from the background information supplied by the inventors: "The present disclosure herein relates to integrated circuit devices, and more particularly, to a nonvolatile memory devices and methods of manufacturing the same.

"Semiconductor devices may be classified into memory devices and logic devices. The memory devices may store data therein. In general, semiconductor memory devices may be classified into volatile memory devices and nonvolatile memory devices. Volatile memory devices may lose data stored therein upon interruption of power supplied thereto. Volatile memory devices may include, for example, dynamic random access memory (DRAM) and static random access memory (SRAM). Nonvolatile memory devices do not lose data stored therein even when power supplied thereto is interrupted. For example, nonvolatile memory devices may include programmable read-only memory (PROM), erasable PROM (EPROM), electrically EPROM (EEPROM), and flash memory devices.

"In order to achieve higher performance and lower power consumption, there have been developed next generation semiconductor memory devices, such as a ferroelectric RAM (FRAM), magnetic RAM (MRAM), and phase-change RAM (PRAM). Materials of such next-generation semiconductor memory devices may be operable to provide varying resistance values in response to a current or a voltage, and may be operable to maintain such programmed resistance values in spite of interruption of the current or the voltage."

In addition to obtaining background information on this patent, VerticalNews editors also obtained the inventors' summary information for this patent: "The present disclosure provides resistance variable memory devices having improved electrical characteristics and reliability and methods of manufacturing the same.

"Objects of the inventive concept are not limited thereto. That is, other objects will be apparently understood from the following description by those skilled in the art.

"Some embodiments of the inventive concept provide a nonvolatile memory device including a substrate and a first insulating layer on the substrate. The first insulating layer includes a first opening therein, and a lower electrode is provided in the first opening and protrudes from a surface of the first insulating layer outside the first opening. An electrode passivation pattern is provided on a sidewall of the lower electrode that protrudes from the surface of the first insulating layer. A second insulating layer is provided on the first insulating layer and includes a second opening therein at least partially exposing the lower electrode. A variable-resistance material layer extends into the second opening to contact the lower electrode, and the electrode passivation layer electrically separates the sidewall of the lower electrode from the variable resistance material layer.

"In some embodiments, the electrode passivation pattern may be formed of a material having an etching selectivity to that of the second insulating layer.

"In some embodiments, the first insulating layer may be formed of a material that does not have an etching selectivity to that of the second insulating layer.

"In some embodiments, a word line may be provided on the substrate. A portion of the word line may be exposed by the first opening in the first insulating layer such that the lower electrode may provide an electrical connection between the word line and the variable resistance material layer.

"In some embodiments, an upper electrode may be provided on the variable resistance material layer opposite the lower electrode, and a bit line may be provided on the upper electrode. The upper electrode may provide an electrical connection between the bit line and the variable resistance material layer.

"In some embodiments, a diode may be provided in the first opening in the first insulating layer electrically contacting the word line. A silicide layer may be provided on the diode such that the silicide layer may be between the lower electrode and the diode.

"In some embodiments, the lower electrode may include a conductive layer on a sidewall of the first opening in the first insulating layer, and a third insulating layer on the conductive layer. The third insulating layer may be formed of a material having an etching selectivity to that of the first insulating layer.

"In some embodiments, the conductive layer may extend on opposing sidewalls of the opening in the first insulating layer, and the third insulating layer may extend between the opposing sidewalls.

"In some embodiments, the electrode passivation layer may include sidewall spacers extending on opposing sidewalls of the conductive layer that protrude outside the first opening in the first insulating layer.

"In some embodiments, the electrode passivation layer may extend on the sidewall of the lower electrode and along the surface of the substrate outside the opening in the first insulating layer.

"In some embodiments, the electrode passivation layer may be a sidewall spacer extending between the lower electrode and the first insulating layer along a sidewall of the first opening therein.

"In some embodiments, the variable resistance material layer may be a phase changeable material layer configured to transition between an amorphous state and a crystalline state responsive to heat applied thereto.

"Additional embodiments of the inventive concept provide a method of fabricating a nonvolatile memory device. The method includes forming a first insulating layer on a substrate, including a first opening in the first insulating layer. A lower electrode is formed in the first opening and protrudes from a surface of the first insulating layer outside the first opening. An electrode passivation layer is formed on a sidewall of the lower electrode that protrudes from the first opening. A second insulating layer is formed on the first insulating layer and includes a second opening therein at least partially exposing the lower electrode. A variable resistance material layer is formed extending into the second opening to contact the lower electrode. The electrode passivation layer electrically separates the sidewall of the lower electrode from the variable resistance material layer.

"In some embodiments, the electrode passivation layer may be formed of a material having an etching selectivity to that of the second insulating layer. The second insulating layer may be selectively etched to form the second opening therein without substantially etching the electrode passivation layer.

"In some embodiments, forming the lower electrode protruding from the surface of the first insulating layer may include forming a conductive layer on a sidewall of the first opening in the first insulating layer, and forming a third insulating layer on the conductive layer. The third insulating layer may be formed of a material having an etching selectivity to that of the first insulating layer. The first insulating layer may be selectively recessed without substantially removing the third insulating layer and the conductive layer.

"In some embodiments, the conductive layer may be formed on opposing sidewalls of the opening in the first insulating layer, and the third insulating layer may be formed on the conductive layer between the opposing sidewalls.

"In some embodiments, the electrode passivation layer may be formed as sidewall spacers extending on opposing sidewalls of the conductive layer that protrude outside the first opening in the first insulating layer.

"In some embodiments, the electrode passivation layer may be formed on the sidewall of the lower electrode and along the surface of the substrate outside the opening in the first insulating layer.

"In some embodiments, the electrode passivation layer may be formed as a sidewall spacer extending along opposing sidewalls of the first opening, and the lower electrode may be formed in the first opening on the sidewall spacer.

"Further embodiments of the inventive concept provide a nonvolatile memory device including a substrate and a word line on the substrate. A first insulating layer is provided on the substrate, and includes a first opening therein at least partially exposing the word line. A diode is provided in the first opening in the first insulating layer and electrically contacting the word line. A silicide layer is provided on the diode, and a lower electrode is provided on the silicide layer in the first opening. The lower electrode protrudes from a surface of the first insulating layer outside the first opening. An electrode passivation pattern is provided on a sidewall of the lower electrode that protrudes from the surface of the first insulating layer. A second insulating layer is provided on the first insulating layer and includes a second opening therein at least partially exposing the lower electrode. The electrode passivation pattern includes a material having an etching selectivity to that of the second insulating layer. A variable resistance material layer is provided extending into the second opening to contact the lower electrode. The electrode passivation layer electrically separates the sidewall of the lower electrode from the variable resistance material layer. An upper electrode is provided on the variable resistance material layer opposite the lower electrode, and a bit line is provided on the upper electrode.

"Still further embodiments of the inventive concept provide methods of manufacturing a resistance variable memory device, the methods including forming a first interlayer dielectric which comprises an opening on a substrate; forming an electrode passivation pattern on a sidewall of the opening; forming a lower electrode which fills the opening; forming a second interlayer dielectric which comprises a recess region exposing an upper surface of the lower electrode on the first interlayer dielectric; and forming a resistance variable material layer in the recess region, wherein the upper surface of the lower electrode is higher than an upper surface of the first interlayer dielectric exposed by the recess region.

"In some embodiments, the electrode passivation pattern may have an etch selectivity with respect to the first interlayer dielectric and the second interlayer dielectric.

"In other embodiments, the forming of the recess region may include removing part of the exposed upper surface of the first interlayer dielectric.

"In still other embodiments, the electrode passivation pattern may be formed by a spacer process.

"In even other embodiments, the resistance variable material layer may cover an upper sidewall of the electrode passivation pattern.

"In other embodiments of the inventive concept, methods of manufacturing a resistance variable memory device include forming a first interlayer dielectric which comprises an opening on a substrate; forming a lower electrode in the opening; recessing the first interlayer dielectric such that an upper sidewall of the lower electrode is exposed; forming an electrode passivation layer which covers the exposed sidewall of the lower electrode on the first interlayer dielectric; forming a second interlayer dielectric on the electrode passivation layer; and forming a recess region which exposes an upper surface of the lower electrode by patterning the second interlayer dielectric, wherein the electrode passivation layer has an etch selectivity with respect to the second interlayer dielectric.

"In some embodiments, the patterning may include patterning the electrode passivation layer and thereby forming an electrode passivation pattern in the form of a spacer which covers the upper sidewall of the lower electrode.

"In other embodiments, the recess region may expose part of an upper surface of the first interlayer dielectric, and the exposed upper surface of the first interlayer dielectric may be lower than the upper surface of the lower electrode.

"In still other embodiments, the method may further include forming a dielectric pattern which fills the opening on the lower electrode, and the dielectric pattern may have an etch selectivity with respect to the first interlayer dielectric and the second interlayer dielectric.

"In even other embodiments, the method may further include forming an electrode passivation pattern which exposes the upper surface of the lower electrode by planarizing the electrode passivation layer.

"In yet other embodiments, the recessing of the first interlayer dielectric may include selectively etching the first interlayer dielectric.

"In further embodiments, the forming of the low electrode may include forming a lower electrode layer on a sidewall and a bottom surface of the opening; forming a third dielectric layer which fills the opening; and planarizing the lower electrode and the third dielectric layer to thereby expose the first interlayer dielectric.

"In still further embodiments, the method may further include forming a mask layer which covers part of the upper surface of the lower electrode; removing part of the upper surface of the lower electrode exposed by the mask layer; and forming a fourth dielectric layer on the removed part.

"In still other embodiments of the inventive concept, resistance variable memory devices include a first interlayer dielectric disposed on a substrate, comprising an opening; a lower electrode disposed in the opening; a second interlayer dielectric disposed on the first interlayer dielectric, comprising a recess region which exposes the lower electrode; an electrode passivation pattern disposed on a sidewall of the lower electrode and made of a material having an etch selectivity with respect to the second interlayer dielectric; and a resistance variable material layer disposed in the recess region.

"In some embodiments, an upper surface of the lower electrode may be disposed higher than an upper surface of the first interlayer dielectric exposed by the recess region.

"In some embodiments, the electrode passivation pattern may have an etch selectivity with respect to the first interlayer dielectric and the second interlayer dielectric.

"In other embodiments, the electrode passivation pattern may be disposed on an inner sidewall of the opening.

"In still other embodiments, an upper surface of the electrode passivation pattern may be coplanar with the upper surface of the lower electrode.

"In even other embodiments, the electrode passivation pattern may be disposed on the first interlayer dielectric.

"In yet other embodiments, the electrode passivation pattern may be in the form of a spacer.

"In further embodiments, an upper surface of the electrode passivation pattern may be coplanar with the upper surface of the lower electrode.

"In still further embodiments, the lower electrode may be a ring type, a half ring type, or a linear type."

For more information, see this patent: Jeong, Ji-Hyun; Oh, JaeHee; Joo, Heung Jin; Eun, Sung-Ho. Variable Resistance Memory Devices Having Reduced Reset Current. U.S. Patent Number 8748884, filed April 6, 2011, and published online on June 10, 2014. Patent URL: http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=8748884.PN.&OS=PN/8748884RS=PN/8748884

Keywords for this news article include: Semiconductor, Random Access Memory, Samsung Electronics Co. Ltd..

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Source: Electronics Newsweekly


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