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Patent Issued for through Wafer Vias and Method of Making Same

June 25, 2014



By a News Reporter-Staff News Editor at Electronics Newsweekly -- From Alexandria, Virginia, VerticalNews journalists report that a patent by the inventors Ding, Hanyi (Essex Junction, VT); Joseph, Alvin J. (Williston, VT); Stamper, Anthony K. (Williston, VT), filed on November 1, 2012, was published online on June 10, 2014.

The patent's assignee for patent number 8748308 is International Business Machines Corporation (Armonk, NY).

News editors obtained the following quote from the background information supplied by the inventors: "To increase the density of devices using integrated circuit chips it is desirable to allow interconnections to be made to both the top and bottom surfaces of the integrated circuit chip. This requires formation of through wafer vias from the top to the bottom surface of the integrated chip that are compatible with carrying both high frequency and DC signals. Many existing through via schemes are either difficult to integrate into existing integrated circuit fabrication processes or result in unacceptable degradation of signals propagating from/to the front surface of the integrated circuit chip to/from the bottom surface of the integrated circuit chip. Accordingly, there exists a need in the art to overcome the deficiencies and limitations described hereinabove."

As a supplement to the background information on this patent, VerticalNews correspondents also obtained the inventors' summary information for this patent: "A first aspect of the present invention is a structure, comprising: a semiconductor substrate having a top surface and an opposite bottom surface; and an array of through wafer vias comprising at least one electrically conductive through wafer via and at least one electrically non-conductive through wafer via, each through wafer via of the array of through wafer vias extending from the top surface of to the bottom surface of the substrate, the at least one electrically conductive via electrically isolated from the substrate.

"A second aspect of the present invention is a method, comprising: forming an array of through wafer vias comprising at least one electrically conductive through wafer via and at least one electrically non-conductive through wafer via, through a semiconductor substrate having a top surface and an opposite bottom surface, each through wafer via of the array of through wafer vias extending from the top surface of to the bottom surface of the substrate, the at least one electrically conductive via electrically isolated from the substrate.

"A third aspect of the present invention is a method, comprising: (a) forming a first trench and a second trench in a semiconductor substrate, the first and second trenches extending in a first direction from a top surface of the substrate toward an opposite bottom surface of the substrate a distance less than a thickness of the substrate in the first direction; after (a), (b) simultaneously forming a first liner of a dielectric material on sidewalls of the first trench and a second liner of the dielectric material on sidewalls of the second trench; after (b), filling remaining space in the first trench with an electrically conductive material and forming a third liner of the electrically conductive material on the second liner, the third liner not completely filling the second trench; after , (d), filling remaining space in the second trench with a polysilicon core, recessing the polysilicon core and the third liner below the top surface of the substrate, and forming, in the second trench, a dielectric plug on the polysilicon core and the third liner; and after (d), (e) thinning the substrate from the bottom surface of the substrate to form a new bottom surface of the substrate, the electrically conductive material of the first trench and the liner and polysilicon core of the second trench exposed in the new bottom surface of substrate.

"A fourth aspect of the present invention is a signal transmission line through a semiconductor substrate, the substrate having a top surface and an opposite bottom surface, comprising: a conductive through via extending from the top surface of the substrate to the bottom surface of the substrate, sidewalls of the conductive through via in physical and electrical contact with the substrate, sidewalls of the conductive through via electrically insulated from the substrate; and a non-conductive through via extending from the top surface of the substrate to the bottom surface of the substrate, the nonconductive through via proximate to and separated from the conductive through wafer via by a region of the substrate, the non-conductive through via comprising a conductive core electrically insulated from the substrate by a dielectric liner and having a dielectric plug recessed between the liner in an end proximate to the top surface of the substrate."

For additional information on this patent, see: Ding, Hanyi; Joseph, Alvin J.; Stamper, Anthony K.. through Wafer Vias and Method of Making Same. U.S. Patent Number 8748308, filed November 1, 2012, and published online on June 10, 2014. Patent URL: http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=8748308.PN.&OS=PN/8748308RS=PN/8748308

Keywords for this news article include: Electronics, Semiconductor, International Business Machines Corporation.

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Source: Electronics Newsweekly


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