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Patent Issued for Super Junction Transistor and Fabrication Method

June 25, 2014



By a News Reporter-Staff News Editor at Electronics Newsweekly -- According to news reporting originating from Alexandria, Virginia, by VerticalNews journalists, a patent by the inventors Lin, Yung-Fa (Hsinchu, TW); Hsu, Shou-Yi (Hsinchu County, TW); Wu, Meng-Wei (Hsinchu, TW); Chen, Main-Gwo (Hsinchu County, TW); Chang, Chia-Hao (Hsinchu, TW); Chen, Chia-Wei (Taipei, TW), filed on March 29, 2012, was published online on June 10, 2014.

The assignee for this patent, patent number 8748973, is Anpec Electronics Corporation (Hsinchu Science Park, Hsin-Chu, TW).

Reporters obtained the following quote from the background information supplied by the inventors: "The present invention generally relates to the field of semiconductor power devices, and more particularly, to a super-junction semiconductor power device with various gate arrangements and a fabrication method thereof.

"A power device is used in power management; for example, in a switching power supply, a management integrated circuit in the core or peripheral region of a computer, a backlight power supply or in an electric motor control. The types of power devices include insulated gate bipolar transistors (IGBT), metal-oxide-semiconductor field effect transistors (MOSFET), and bipolar junction transistors (BJT), among which the MOSFETs are the most widely applied because of their energy saving properties and their ability to provide faster switching speeds.

"In one kind of power MOSFET device, two kind of epitaxial layers, one with a first conductivity type and the other one with a second conductivity type, are disposed alternatively to form several PN junctions inside a body. The junctions are orthogonal to a surface of the body and the device with such PN junctions is also called a super-junction power MOSFET device. In addition, in order to control the on-off state of current transmitting in devices, a plurality of gate structure units is disposed on a cell region of the device. But in a conventional super-junction power device, some drawbacks still need to be overcome. For example, each of the gate structure units usually has non-rounded corner, which may reduce the voltage sustaining ability of the device. In addition, this kind of gate structure unit layout is not good enough to meet the requirement of various products.

"In light of the above, there is still a need for providing a structure and a method for fabricating an improved super-junction power MOSFET, which has to be capable of overcoming the shortcomings and deficiencies of the prior art."

In addition to obtaining background information on this patent, VerticalNews editors also obtained the inventors' summary information for this patent: "One objective of the invention is therefore to provide super-junction power devices with various layouts of gate structure units and a fabrication method thereof that has a better voltage sustaining ability, compared to conventional power devices so that the power devices can meet the requirement of various kinds of products.

"To this end, the invention provides a super junction transistor comprising the following components. A drain substrate having a first conductivity type; an epitaxial layer having a second conductivity type, wherein the epitaxial layer is disposed on the drain substrate; a plurality of gate structure units embedded on the surface of the epitaxial layer; a plurality of trenches disposed in the epitaxial layer between the drain substrate and the gate structure units; a buffer layer in direct contact with the interior surface of the trenches; a plurality of body diffusion regions with a first conductivity type adjacent to the outer surface of the trenches, wherein there is at least a PN junction on the interface between the body diffusion region and the epitaxial layer; and a doped source region, wherein the doped source region is disposed in the epitaxial layer and is adjacent to the gate structure unit.

"According to another embodiment, a super junction transistor is provided, which comprises: a drain substrate having a first conductivity type; an epitaxial layer having a second conductivity type, wherein the epitaxial layer is disposed on the drain substrate; a plurality of doped source units having the first conductivity type, wherein the doped source units are embedded on the surface of the epitaxial layer; a gate structure embedded on the surface of the epitaxial layer, wherein the gate structure is adjacent to the doped source units; a plurality of trenches disposed in the epitaxial layer between the drain substrate and the doped source units; a buffer layer in direct contact with the interior surface of the trenches; and a plurality of body diffusion regions with a first conductivity type adjacent to the outer surface of the trenches, wherein there is at least a PN junction on interface between the body diffusion region and the epitaxial layer.

"According to another embodiment, a method of fabricating a super junction transistor is provided, which comprises the following steps. A drain substrate having a first conductivity type is provided. An epitaxial layer is formed on the drain substrate, wherein the epitaxial layer has a second conductivity type. A plurality of trenches is formed in the epitaxial layer. A buffer layer is formed and is in direct contact with the interior surface of the trenches. A dopant source layer is filled into the trenches, wherein the dopant source layer has at least dopants with the first conductivity type. An etching process is performed to form a plurality of recessed structures above the respective trenches. A gate oxide layer is formed on the surface of each recessed trench and the dopants inside the dopant source layer are diffused into the epitaxial layer through the buffer layer to thereby form at least a body diffusion layer of the first conductivity type. A gate conductor is filled into the recessed structures to form a plurality of gate structure units. A doped source region having the first conductivity type is formed, wherein the doped source region is disposed in the epitaxial layer and is adjacent to each gate structure unit.

"These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings."

For more information, see this patent: Lin, Yung-Fa; Hsu, Shou-Yi; Wu, Meng-Wei; Chen, Main-Gwo; Chang, Chia-Hao; Chen, Chia-Wei. Super Junction Transistor and Fabrication Method. U.S. Patent Number 8748973, filed March 29, 2012, and published online on June 10, 2014. Patent URL: http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=8748973.PN.&OS=PN/8748973RS=PN/8748973

Keywords for this news article include: Semiconductor, Anpec Electronics Corporation.

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Source: Electronics Newsweekly


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