The assignee for this patent, patent number 8749296, is
Reporters obtained the following quote from the background information supplied by the inventors: "The prior art for a biasing arrangement of base and body contacts for a stacked shunt switch is depicted in FIGS. 1, 2, and 3. FIG. 1 depicts the gate connections for a stacked SOI switch using floating bodies. FIG. 2 depicts the gate and body biasing connections for a stacked structure and is applicable to both SOI and bulk technologies. FIG. 3 is similar to FIG. 2 but further includes drain-source resistors.
"In a front end switch design targeted at cellular applications, the number of stacked devices could easily exceed 10 and the value of the R.sub.GATE, R.sub.BODY and R.sub.DS resistors may be greater than 50 kohm. The value of the R.sub.GATE and R.sub.BODY and R.sub.DS resistors are chosen to be high enough to give an even distribution of any RF signal across each of the transistors when the switch is in its `off` state but also low enough to meet switching time requirements.
"The problem with this approach comes with the resistors. As the switch is split into N segments, N resistors of value N times the value used in the original resistors in the switch design are needed. This can lead to a requirement for a large number of very high value resistors resulting in significant area penalties.
"Accordingly, there is a need to develop a stacked SOI switch that permits the use of smaller valued resistors."
In addition to obtaining background information on this patent, VerticalNews editors also obtained the inventor's summary information for this patent: "Embodiments in the detailed description include a serial stacked shunt semiconductor on insulator (SOI) switch series that distributes the drain-source voltage across each of the FET devices when the FET devices are in an off state.
"An example serial stacked shunt semiconductor on insulator (SOI) switch includes a plurality of FET devices. Each FET device includes a gate contact, a drain contact, and a source contact. The plurality of FET devices are coupled in series to form a chain having a first drain at a first end of the chain, a first source coupled at a second end of the chain, and where the gate contact of the FET device at the second end of the chain is a first gate contact. A plurality of gate biasing circuits coupled in series, wherein each of the plurality of gate biasing circuits is coupled between a corresponding pair of gate contacts of the plurality of FET devices. In addition, a common biasing circuit has a first terminal and a second terminal, wherein the first terminal is coupled to the first gate contact.
"One benefit of the serial stacked shunt SOI switch topology is that the off state loading of each gate biasing resistors in a stacked FET structure is substantially reduced. As a result, the values of the bias resistors may be substantially reduced. Because the value of a resistor on an integrated chip is directly related to surface area dedicated to the resistor, the reduction in the values of the bias resistors permits a substantial reduction in the area attributed to the bias resistors. The series stacked FET structure also has the added benefit of evenly distributing the drain-source voltage across each of the FET devices when the FET devices are in the off state.
"Those skilled in the art will appreciate the scope of the disclosure and realize additional aspects thereof after reading the following detailed description in association with the accompanying drawings."
For more information, see this patent: Granger-
Keywords for this news article include: Electronics, Semiconductor,
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