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Patent Issued for Shape Simulation Apparatus, Shape Simulation Program, Semiconductor Production Apparatus, and Semiconductor Device Production Method

June 25, 2014



By a News Reporter-Staff News Editor at Electronics Newsweekly -- According to news reporting originating from Alexandria, Virginia, by VerticalNews journalists, a patent by the inventors Kuboi, Nobuyuki (Tokyo, JP); Kinoshita, Takashi (Kanagawa, JP); Tatsumi, Tetsuya (Kanagawa, JP), filed on August 21, 2013, was published online on June 10, 2014.

The assignee for this patent, patent number 8747685, is Sony Corporation (Tokyo, JP).

Reporters obtained the following quote from the background information supplied by the inventors: "The present invention relates to a shape simulation apparatus, a shape simulation program, a semiconductor production apparatus, and a semiconductor device production method.

"There exist techniques for simulating the wafer surface shape that varies with etching and deposition. Japanese Patent Laid-open No. 2009-152269 (hereinafter referred to as Patent Document 1) illustratively discloses a simulation method that takes into account of how the aperture ratio of the wafer and the effective solid angles of local patterns affect plasma etching. The wafer aperture ratio and the effective solid angles of local patterns will be discussed later. Taking the effects of these parameters into account makes it possible to consider three-dimensionally the effects of the shape of mask patterns on two-dimensional simulation."

In addition to obtaining background information on this patent, VerticalNews editors also obtained the inventors' summary information for this patent: "Experiments conducted by the inventors confirmed that when a plurality of patterns of the same shape (e.g., gate electrodes) are etched, there occur dimensional discrepancies between the actual products even if the wafer aperture ratio and effective solid angle are the same for the multiple patterns involved. Hence the need for clarifying any additional factors affecting the product dimensions in order to improve the accuracy of shape prediction.

"The present invention has been made in view of the above circumstances and provides a shape simulation apparatus, a shape simulation program, a semiconductor production apparatus, and a semiconductor device production method for improving the accuracy of shape simulation.

"In carrying out the present invention and according to one embodiment thereof, there is provided a shape simulation apparatus including: a flux computation block configured to compute the flux of particles incident on the surface of a wafer covered with a mask; and a shape computation block configured to compute a surface shape of the wafer by allowing the coordinates of a plurality of calculation points established on the surface of the wafer to be time-evolved based on the incident flux computed. In the shape simulation apparatus, the flux computation block computes the incident flux based on a solid angle, as seen from the calculation point of interest, of that range of a local region which includes the calculation point of interest and which is left unshielded by any pattern inside the local region; on a wafer aperture ratio of the aperture area of the mask to the area of the mask; and on a semilocal aperture ratio of the aperture area of the mask over the semilocal region to the area of a semilocal region which includes the local region and which is narrower than the wafer.

"Preferably, the flux computation block may compute a distribution of the incident fluxes based on a distribution of the solid angles, on the wafer aperture ratio, and on a distribution of the semilocal aperture ratios; and the shape computation block may compute a three-dimensional surface shape based on the distribution of the incident fluxes.

"Preferably, the flux computation block may compute the incident flux in such a manner that of the incident fluxes, those attributable to an etched film become proportional to the solid angles as well as to the sum of the wafer aperture ratios and the semilocal aperture ratios.

"Preferably, the local region and the semilocal region may be established in a manner centering on each of the calculation points.

"Preferably, the shape simulation apparatus of the embodiment of the present invention may further include a semilocal aperture ratio map creation block configured to store a plurality of calculation points in association with a plurality of semilocal aperture ratios into a storage block; wherein the flux computation block may compute the incident flux by referencing the plurality of semilocal aperture ratios stored in the storage block.

"Preferably, the wafer may have a plurality of chip regions disposed thereon; and the semilocal region may be established to be smaller than each of the plurality of chip regions.

"Preferably, the radius of the semilocal region may be larger than a mean free path of any one of the particles.

"According to another embodiment of the present invention, there is provided a shape simulation program including the steps of: causing a computer to function as a flux computation block computing the flux of particles incident on the surface of a wafer covered with a mask; and causing the computer to function as a shape computation block computing a surface shape of the wafer by allowing the coordinates of a plurality of calculation points established on the surface of the wafer to be time-evolved based on the incident flux computed. In the program, the flux computation block is caused to compute the incident flux based on a solid angle, as seen from the calculation point of interest, of that range of a local region which includes the calculation point of interest and which is left unshielded by any pattern inside the local region; on a wafer aperture ratio of the aperture area of the mask to the area of the mask; and on a semilocal aperture ratio of the aperture area of the mask over the semilocal region to the area of a semilocal region which includes the local region and which is narrower than the wafer.

"According to a further embodiment of the present invention, there is provided a semiconductor production apparatus including: a detection section configured to detect parameters of an etching process being performed on a wafer covered with a mask; a simulation section configured to perform a simulation of a surface shape of the wafer; and a control section configured to acquire results of the simulation performed by the simulation section in keeping with the parameters detected by the detection section, so as to correct the etching parameters based on the acquired simulation results. In the semiconductor production apparatus, the simulation section includes: a flux computation block configured to compute the flux of particles incident on the surface of the wafer; and a shape computation block configured to compute the surface shape of the wafer by allowing the coordinates of a plurality of calculation points established on the surface of the wafer to be time-evolved based on the incident flux computed. The flux computation block computes the incident flux based on a solid angle, as seen from the calculation point of interest, of that range of a local region which includes the calculation point of interest and which is left unshielded by any pattern inside the local region; on a wafer aperture ratio of the aperture area of the mask to the area of the mask; and on a semilocal aperture ratio of the aperture area of the mask over the semilocal region to the area of a semilocal region which includes the local region and which is narrower than the wafer.

"According to an even further embodiment of the present invention, there is provided a semiconductor device production method including the steps of: detecting parameters of an etching process being performed on a wafer covered with a mask; performing a simulation of a surface shape of the wafer; and acquiring results of the simulation performed in the simulation performing step in keeping with the parameters detected in the detecting step, so as to correct the etching parameters based on the acquired simulation results. The simulation performing step includes: computing the flux of particles incident on the surface of the wafer; and computing the surface shape of the wafer by allowing the coordinates of a plurality of calculation points established on the surface of the wafer to be time-evolved based on the incident flux computed. The flux computing step computes the incident flux based on a solid angle, as seen from the calculation point of interest, of that range of a local region which includes the calculation point of interest and which is left unshielded by any pattern inside the local region; on a wafer aperture ratio of the aperture area of the mask to the area of the mask; and on a semilocal aperture ratio of the aperture area of the mask over the semilocal region to the area of a semilocal region which includes the local region and which is narrower than the wafer.

"According to the present inventions outlined above, the accuracy of simulations is improved."

For more information, see this patent: Kuboi, Nobuyuki; Kinoshita, Takashi; Tatsumi, Tetsuya. Shape Simulation Apparatus, Shape Simulation Program, Semiconductor Production Apparatus, and Semiconductor Device Production Method. U.S. Patent Number 8747685, filed August 21, 2013, and published online on June 10, 2014. Patent URL: http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=8747685.PN.&OS=PN/8747685RS=PN/8747685

Keywords for this news article include: Electronics, Semiconductor, Sony Corporation.

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Source: Electronics Newsweekly


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