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Patent Issued for Sense-Amp Transistor of Semiconductor Device and Method for Manufacturing the Same

June 25, 2014



By a News Reporter-Staff News Editor at Electronics Newsweekly -- Hynix Semiconductor Inc. (Icheon, KR) has been issued patent number 8748978, according to news reporting originating out of Alexandria, Virginia, by VerticalNews editors.

The patent's inventor is Lee, Sang Ho (Yongin-si, KR).

This patent was filed on January 10, 2012 and was published online on June 10, 2014.

From the background information supplied by the inventors, news correspondents obtained the following quote: "Embodiments of the present invention relate to a sense-amp transistor of a semiconductor device, and more particularly to a sense-amp transistor of a semiconductor device and a method for manufacturing the same, which can minimize the number of additional processes by improving a gate structure of the sense-amp transistor, thus increasing a sensing margin.

"A sense amplifier (hereinafter referred to as a sense-amp) of a semiconductor device includes a pull-up element using a PMOS transistor and a pull-down element using an NMOS transistor, such that it amplifies a data voltage loaded on a bit line (BL) and a bit line bar (/BL) and outputs the amplified result to a data bus.

"FIG. 1 is a circuit diagram illustrating a pull-up element and a pull-down element of a sense-amp for use in a semiconductor device.

"Referring to FIG. 1, the sense-amp of the semiconductor device includes PMOS transistors (P1, P2) and NMOS transistors (N1, N2), that are complementarily coupled to one another in the form of a cross-coupled latch between a pull-up voltage (RTO) and a pull-down voltage (SB). A gate of the PMOS transistor P1 and a gate of the NMOS transistor N1 are coupled to a bit line (BL), and a commonly connected drain of the PMOS and NMOS transistors P1 and N1 is coupled to a bit line bar (/BL). A gate of the PMOS transistor P2 and a gate of the NMOS transistor N2 are coupled to the bit line bar (/BL), and a commonly connected drain of the PMOS and NMOS transistors P2 and N2 is coupled to the bit line (BL).

"FIG. 2 is a plan view illustrating a sense-amp shown in FIG. 1.

"Referring to FIG. 2, an active region 10, in which four transistors are to be formed, is formed in a square shape, and a gate of each transistor constructing the sense-amp is in a ring shape in the active region 10.

"Transistors constructing the sense-amp shown in FIG. 2 have been designed to use a recess gate structure to increase a current.

"However, recently, as the integration degree of semiconductor devices increase and cell size gradually shrinks, the sense-amp area also shrinks.

"However, since a conventional sense-amp allows a gate of each transistor to be configured in the form of a recess gate, and uses a ring-type gate structure as the recess gate, it is difficult to shrink the sense-amp area.

"In addition, in the conventional sense-amp a channel was formed only in a recessed channel region, so that it may be difficult to guarantee the sensing margin when the size of the semiconductor device is reduced."

Supplementing the background information on this patent, VerticalNews reporters also obtained the inventor's summary information for this patent: "Various embodiments of the present invention are directed to providing a sense-amp transistor of a semiconductor device and a method for manufacturing the same that substantially obviate one or more problems due to limitations and disadvantages of the related art.

"An embodiment of the present invention relates to a sense-amp transistor of a semiconductor device and a method for manufacturing the same, which can minimize the number of additional processes by improving a sense-amp transistor structure, resulting in a guarantee of a sensing margin of the sense-amp.

"In accordance with an aspect of the present invention, a sense-amp transistor for a semiconductor device includes a recess array formed in a gate region of a sense-amp; a plurality of buried gates formed in each recess of the recess array so as to form a vertical channel region; and an upper gate configured to form a horizontal channel region in an active region between the buried gates.

"The buried gate may include metal.

"The upper gate may be formed not only over the buried gates but also over the active region between the buried gates in such a manner that the upper gate is electrically coupled to the buried gates. The upper gate may be formed of polysilicon.

"The buried gates may be simultaneously formed when a cell-burying gate of a cell region is formed.

"The recess formed at both ends of the recess array may be formed to contact an active region and a device isolation film. The recess array may be formed as a line type, and each active region of the sense-amp region includes two recess arrays arranged in parallel to each other.

"In accordance with another aspect of the present invention, a method for manufacturing a sense-amp transistor includes forming a recess array in a gate region of a sense-amp in such a manner that recesses are arranged in a line; forming at least one buried gate in the recess; and forming an upper gate not only over the buried gates but also over the active region between the buried gates.

"The forming of the recess array may be performed simultaneously while forming a recess for a cell-burying gate in a cell region. The forming of the at least one buried gate may be performed simultaneously while forming the cell-burying gate in the recess for the cell-burying gate

"The forming of the recess array may include forming a device isolation film defining an active region in a sense-amp region; and forming the plurality of recesses by etching the active region of the buried gate region and the device isolation film, wherein the device isolation film is etched when the recess located at both ends of the recess array is formed.

"The forming of the upper gate may include forming a polysilicon layer not only over the active region including an upper part of the buried gate but also over an upper part of the device isolation film; patterning the polysilicon layer using a mask defining the gate region; and implanting N.sup.+ ions in the polysilicon layer of an NMOS region from among the gate region and implanting P.sup.+ ions in a PMOS region from among the gate region.

"The method may further include forming a source and a drain by implanting impurities in an exposed active region located at both sides of the upper gate.

"It is to be understood that both the foregoing general description and the following detailed description of the present invention are exemplary and explanatory and are intended to provide further explanation of the invention as claimed."

For the URL and additional information on this patent, see: Lee, Sang Ho. Sense-Amp Transistor of Semiconductor Device and Method for Manufacturing the Same. U.S. Patent Number 8748978, filed January 10, 2012, and published online on June 10, 2014. Patent URL: http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=8748978.PN.&OS=PN/8748978RS=PN/8748978

Keywords for this news article include: Electronics, Hynix Semiconductor Inc..

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Source: Electronics Newsweekly


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