News Column

Patent Issued for Semiconductor Memory Apparatus

June 25, 2014



By a News Reporter-Staff News Editor at Journal of Engineering -- SK Hynix Inc. (Gyeonggi-do, KR) has been issued patent number 8750064, according to news reporting originating out of Alexandria, Virginia, by VerticalNews editors.

The patent's inventor is Kim, So Jeong (Icheon-si, KR).

This patent was filed on December 30, 2011 and was published online on June 10, 2014.

From the background information supplied by the inventors, news correspondents obtained the following quote: "The present invention relates generally to a semiconductor integrated circuit, and more particularly to a semiconductor memory apparatus.

"A semiconductor memory apparatus refers to an apparatus that can store data and output the stored data in response to a request from a controller. More specifically, the semiconductor memory apparatus stores data using, for example, one transistor and one capacitor as a unit cell.

"Since a known semiconductor memory apparatus such as a DRAM stores data using charging/discharging of a capacitor, the capacitor should be recharged at every predetermined time. In this case, the operation of recharging at every predetermined time is referred to as a refresh operation."

Supplementing the background information on this patent, VerticalNews reporters also obtained the inventor's summary information for this patent: "A semiconductor memory apparatus capable of reducing current consumption in a refresh operation is described herein.

"In one embodiment of the present invention, a semiconductor memory apparatus includes a first switch configured to connect/separate a bit line and a sense amplifier to/from each other in response to a first bit line separation signal, a second switch configured to connect a bit line bar and the sense amplifier to each other in response to a second bit line separation signal, and a control unit configured to generate a bit line separation signal for refresh, of which enable period is shorter than that of the second bit line separation signal, and provide the generated bit line separation signal for refresh to the second switch in a refresh operation.

"In another embodiment of the present invention, a semiconductor memory apparatus includes a bit line, a bit line bar, a sense amplifier, and a control unit configured to connect one selected from the bit line and the bit line bar to the sense amplifier during a period when the sense amplifier is activated, and connect the other selected from the bit line and the bit line bar to the sense amplifier during a period shorter than that when the sense amplifier is activated, in a refresh operation.

"In still another embodiment of the present invention, a semiconductor memory apparatus includes a first bit line configured to provide data of a first mat when a first word line is enabled, a second bit line configured to provide data of a first mat when a second word line is enabled, a sense amplifier configured to sense and amplify voltage levels of the first and second bit lines in response to a sense amplifier enable signal, a first switch configured to connect the first bit line and the sense amplifier to each other when a first bit line separation signal is enabled, a second switch configured to connect the second bit line and the sense amplifier to each other when a second bit line separation signal is enabled, and a control unit configured to disable the first and second bit line separation signals until the word line is enabled and the sense amplifier enable signal is enabled, enable the first and second bit line separation signals when the sense amplifier enable signal is enabled, disable the enabled second bit line separation signal after a predetermined time elapses, and enable the second bit line separation signal when the sense amplifier enable signal is disabled, in a refresh operation.

"In still another embodiment of the present invention, a semiconductor integrated circuit includes a line configured to transmit a signal, an amplification unit configured to sense and amplify an input voltage during an enable period of an enable signal, a switch configured to input a voltage of the line as the input voltage to the amplification unit when a control signal is enabled, and prevent the voltage of the line from being inputted to the amplification unit when the control signal is disabled, and a control unit configured to enable the control signal when the enable signal is enabled, and generate the control signal of which enable period is shorter than that of the enable signal, in a specific operation mode."

For the URL and additional information on this patent, see: Kim, So Jeong. Semiconductor Memory Apparatus. U.S. Patent Number 8750064, filed December 30, 2011, and published online on June 10, 2014. Patent URL: http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=8750064.PN.&OS=PN/8750064RS=PN/8750064

Keywords for this news article include: Electronics, SK Hynix Inc., Semiconductor.

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Source: Journal of Engineering


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