News Column

Patent Issued for Semiconductor Integrated Circuit Apparatus Having I/O Signal Line

June 25, 2014



By a News Reporter-Staff News Editor at Electronics Newsweekly -- A patent by the inventor Kim, Sung Ho (Gyeonggi-do, KR), filed on September 3, 2012, was published online on June 10, 2014, according to news reporting originating from Alexandria, Virginia, by VerticalNews correspondents.

Patent number 8749302 is assigned to SK Hynix Inc. (Gyeonggi-do, KR).

The following quote was obtained by the news editors from the background information supplied by the inventors: "The present invention relates to a semiconductor integrated circuit apparatus having an I/O signal line, and more particularly, to a local sense amplifier having an I/O signal line.

"With the increase in integration density of semiconductor integrated circuits, I/O signal lines are hierarchically designed.

"For example, DRAM (dynamic random access memory) includes I/O signal lines which are hierarchically divided into global I/O lines GIO, local I/O lines LIO, and segment I/O lines SIO such that signals are transmitted for the respective levels.

"A segment I/O line is connected to a bit line to transmit a signal, and is electrically connected to a local I/O line LIO to transmit a signal. Furthermore, the local I/O line LIO is electrically connected to a global I/O line GIO to transmit a signal.

"In general, a local sense amplifier includes local I/O lines LIO and segment I/O lines which are alternately arranged with column select signal lines interposed therebetween. Furthermore, an upper local I/O line and an upper segment I/O line are extended to the top portions of the local I/O line and the segment I/O line so as to be secondarily connected to a lower local I/O line and a lower segment I/O line. The upper local I/O line and the upper segment I/O line may be arranged in a direction perpendicular to the lower local I/O line and the lower segment I/O line.

"However, as the integration density exponentially increases, the I/O signal lines of the conventional memory apparatus, that is, local I/O lines, segment I/O lines, and column select lines are arranged with a minimum critical dimension (CD) provided therebetween. Since there is a shrinking amount of space to allocate the increasing number of lines, there are difficulties in securing a space for forming a power mesh line."

In addition to the background information obtained for this patent, VerticalNews journalists also obtained the inventor's summary information for this patent: "In one embodiment of the present invention, a semiconductor integrated circuit apparatus includes: a plurality of column select signal lines extended in parallel to each other with a predetermined distance provided therebetween; a local I/O line arranged in a selected space among spaces formed between the respective column select signal lines; and an upper segment I/O line arranged to overlap the local I/O line and a local I/O line bar.

"In another embodiment of the present invention, a semiconductor integrated circuit apparatus includes: a lower segment I/O line and a lower segment I/O line bar extended in parallel to a first direction with a predetermined distance provided therebetween; a plurality of column select signal lines arranged to cross the lower segment I/O line and the lower segment I/O line bar and extended in parallel to each other with a predetermined distance provided therebetween, thereby defining first to fourth spaces; a local I/O line arranged in the first space among the spaces corresponding to the distances between the respective column select signal lines; a local I/O line bar arranged in the second space among the spaces corresponding to the distances between the respective column select signal lines; an upper segment I/O line formed in the first space so as to partially overlap the local I/O line; an upper segment I/O line bar formed in the second space so as to partially overlap the local I/O line; and power mesh lines arranged in the third and fourth spaces, respectively.

"In another embodiment of the present invention, a semiconductor integrated circuit apparatus includes: a semiconductor substrate; a lower segment I/O line and a lower segment I/O line bar formed of a first metal layer over the semiconductor substrate and extended in parallel to a first direction with a predetermined distance provided therebetween; a plurality of column select signal lines formed of a second metal layer, arranged to cross the lower segment I/O line and the lower segment I/O line bar, and extended in parallel to each other with a predetermined distance provided therebetween, thereby defining first to fourth spaces; a local I/O line formed of the second metal layer and arranged in the first space among the spaces corresponding to the distances between the respective column select signal lines; a local I/O line bar formed of the second metal layer and arranged in the second space among the spaces corresponding to the distances between the respective column select signal lines; an upper segment I/O line formed of a third metal layer and formed in the first space so as to partially overlap the local I/O line; an upper segment I/O line bar formed of the third metal layer and formed in the second space so as to partially overlap the local I/O line bar; and power mesh lines arranged in the third and fourth spaces, respectively, wherein insulating layer are interposed between the semiconductor substrate and the first metal layer, between the first metal layer and the second metal layer, and between the second metal layer and the third metal layer, respectively.

"The semiconductor integrated circuit apparatus may further include a first transmission transistor positioned between the lower segment I/O line and the lower segment I/O line bar and configured to transmit a signal of the upper segment I/O line to the local I/O line; and a second transmission transistor positioned between the lower segment I/O line and the lower segment I/O line bar and configured to transmit a signal of the upper segment I/O line bar to the local I/O line bar.

"The lower segment I/O line may be electrically isolated at intersections with the column select signal lines, and electrically connected to the upper segment I/O line.

"Each of the column select signal lines may include a pair of unit column select signal lines."

URL and more information on this patent, see: Kim, Sung Ho. Semiconductor Integrated Circuit Apparatus Having I/O Signal Line. U.S. Patent Number 8749302, filed September 3, 2012, and published online on June 10, 2014. Patent URL: http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=8749302.PN.&OS=PN/8749302RS=PN/8749302

Keywords for this news article include: Electronics, SK Hynix Inc., Semiconductor.

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Source: Electronics Newsweekly


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