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Patent Issued for Semiconductor Device Generating Varied Internal Voltages

June 25, 2014



By a News Reporter-Staff News Editor at Electronics Newsweekly -- From Alexandria, Virginia, VerticalNews journalists report that a patent by the inventors Han, Dong Hoon (Daejeon Metropolitan, KR); Lee, Woo Young (Gyeonggi-do, KR), filed on September 8, 2008, was published online on June 10, 2014.

The patent's assignee for patent number 8749299 is Hynix Semiconductor Inc. (Kyoungki-do, KR).

News editors obtained the following quote from the background information supplied by the inventors: "The present invention relates generally to a semiconductor device, and more particularly to a semiconductor device which generates internal voltages having different levels using an external voltage.

"Generally, a semiconductor device such as DRAM generates and uses various internal power sources using an external power as a source. For example, in order to transfer data stored in a memory cell to a bit line without a voltage drop due to a threshold voltage, a DRAM generates a pumping voltage having a higher voltage level than that of the an external voltage by pumping the supplied external voltage. The DRAM then provides the generated pumping voltage to a word line.

"A conventional circuit which generates such an internal voltage may be provided, as shown in FIG. 1, with a core voltage generating circuit 10 which generates a core voltage VCORE and a pumping voltage generating circuit 20 which generates a pumping voltage VPP.

"The core voltage generating circuit 10 includes an activating unit 12 which outputs an activation signal VCORE_ACT in response to an external command signal, i.e. a RAS command signal RASB. The core voltage generating circuit 10 also includes a detecting unit 14 which compares and detects a potential difference between the core voltage VCORE fed back to the detecting unit 14 and a reference voltage VREF1 in response to the activation signal VCORE_ACT and outputs the detection result as a drive signal DRV. The core voltage generating circuit 10 includes a driving unit 16 which generates the core voltage VCORE by driving an external voltage VEXT in response to the drive signal DRV.

"The pumping voltage generating circuit 20 includes an activating unit 22 which outputs an activation signal VPP_ACT in response to the RAS command signal RASB. The pumping voltage generating circuit 20 also includes a detecting unit 24 which compares and detects a potential difference between the pumping voltage VPP fed back to the detecting unit 24 and a reference voltage VREF2 in response to the activation signal VPP_ACT and outputs the detection result as a drive signal PPEA. The pumping voltage generating circuit 20 includes a pumping unit 26 which generates the pumping voltage VPP by pumping the external voltage VEXT in response to the drive signal PPEA.

"The conventional semiconductor device including the internal voltage generating circuits 10 and 20 as described above activates a word line WL by supplying the pumping voltage VPP when an active command ACT is inputted synchronously with a clock signal CLK, and develops a bit line pair BL and /BL by supplying the core voltage VCORE after a charge sharing as shown in FIG. 2A.

"At this time, the pumping voltage VPP level may drop as the pumping voltage VPP is supplied to the word line WL. The level pumping of the pumping voltage VPP may be performed after a point `T2` as the detecting unit 24 cannot detect this drop of the pumping voltage VPP level within the period `T3`.

"In other words, as shown in FIG. 2B, when the pumping voltage VPP level drops below the reference voltage VREF2 level at point `T1`, the pumping voltage VPP level is raised via the detecting unit 24 and the pumping unit 26. At this time, a series of operations occur including, detecting the level drop of the pumping voltage VPP at `T1` through the detecting unit 24. The drive signal PPEA is then enabled and the pumping voltage VPP level is pumped through the pumping unit 26 which takes longer than a period `T3`. Thus, the pumping of the pumping voltage VPP level is actually performed after `T2`. The external voltage VEXT is consumed after `T2` by the pumping of the pumping voltage VPP level.

"Also, the driving unit 16 consumes the external voltage VEXT to maintain the core voltage VCORE level at the reference voltage VREF1 since the core voltage VCORE is supplied to the bit line BL or the bit bar line BLB from the point `T2`. In other words, after the point `T2`, the external voltage VEXT level drops due to the use of the core voltage VCORE.

"As such, in the conventional semiconductor device, the level drop of the external voltage VEXT due to the pumping of the pumping voltage VPP and the level drop of the external voltage VEXT due to the driving of the core voltage VCORE are generated almost simultaneously with respect to the point `T2`.

"However, when the external voltage VEXT is used in duplicate for the pumping of the pumping voltage VPP and the driving of the core voltage VCORE, a peak value of the external voltage VEXT level drop is instantly increased. This increase may generate a large amount of noise in the external voltage VEXT.

"In this case, problems including the lowering of chip properties may occur eventually leading to a malfunction of the semiconductor chip."

As a supplement to the background information on this patent, VerticalNews correspondents also obtained the inventors' summary information for this patent: "There is provided a semiconductor device which can reduce a peak level drop of an external voltage due to generation of internal voltages.

"Also, there is provided a semiconductor device which can prevent a malfunction due to generation of a noise in an external voltage.

"According to a first embodiment of the present invention, there is provided a semiconductor device, which includes a plurality of asynchronous internal voltage generating circuits sharing an external voltage and generating internal voltages having different levels from one another, wherein at least one of the plurality of asynchronous internal voltage generating circuits generates the internal voltage having a predetermined target level at a point different from that of the rest asynchronous internal voltage generating circuits by using the external voltage.

"Preferably, the plurality of the internal voltage generating circuits are supplied with the external voltage at different points from one another and compensate level drops according to the uses of the internal voltages, thereby maintaining the levels of the internal voltages to the target levels, respectively.

"Preferably, the plurality of the asynchronous internal voltage generating circuits includes a first asynchronous internal voltage generating circuit generating a first internal voltage usable in a circuit using the external voltage and maintaining the first internal voltage to its target level by being supplying with the external voltage when the first internal voltage is used in the circuit; and a second asynchronous internal voltage generating circuit generating a second internal voltage usable in the circuit using the external voltage and maintaining the second internal voltage to its target level by being supplying with the external voltage before the first internal voltage is used in the circuit.

"Preferably, the first asynchronous internal voltage generating circuit generates the first internal voltage and maintains the level of the generated first internal voltage by driving the external voltage, and the second asynchronous internal voltage generating circuit generates the second internal voltage and maintains the level of the generated second internal voltage by pumping the external voltage.

"Preferably, the first and second asynchronous internal voltage generating circuits generate the first and second internal voltages and maintain the generated the first and second internal voltages by pumping the external voltage.

"Preferably, the plurality of the asynchronous internal voltage generating circuits includes a first asynchronous internal voltage generating circuit generating a first internal voltage having a level substantially the same as its target level with the external voltage and maintaining the first internal voltage to the target level with the external voltage when the fed back first internal voltage is out of the target level; and a plurality of second asynchronous internal voltage generating circuits sequentially generating second internal voltages having levels higher than their target levels using the external voltage and maintaining the second internal voltages to the target levels with the external voltage when the fed back second internal voltages are lowered below the target levels, respectively.

"Preferably, the respective second asynchronous internal voltage generating circuit includes an initial overdrive control unit generating an initial overdrive signal; and an internal voltage generating circuit generating the second internal voltage having the level higher than its target level by initially operating with the external voltage in response to the initial overdrive signal and maintaining the second internal voltage to the target level voltage by successively operating with the external when the level of the second internal voltage is lowered below the target level.

"Preferably, the initial overdrive control unit receives the activation signal which operates the second asynchronous internal voltage generating circuit and thus generates the initial overdrive signal having a predetermined pulse and provides the generated initial overdrive signal to the internal voltage generating circuit, and the initial operation period of the internal voltage generating circuit is determined in correspondence to the pulse width of the initial overdrive signal.

"Preferably, the first asynchronous internal voltage generating circuit generates and maintains the first internal voltage by driving the external voltage, and the second asynchronous internal voltage generating circuits generate and maintain the second internal voltages by pumping the external voltage, respectively.

"Preferably, the plurality of the asynchronous internal voltage generating circuits commonly receive an external command signal, and initial activation points of the plurality of the asynchronous internal voltage generating circuits are determined by the external command signal.

"According to a second embodiment of the present invention, there is provided a semiconductor device, which includes a drive control unit receiving an external control signal and fed back internal voltages and outputting a plurality of drive signals having different enabled periods from one another according to a status of the external control signal and detection results of the level of the fed back internal voltages; and a plurality of internal voltage generating units sharing the external voltage and generating the internal voltages with the external voltage in response to the enablement of the drive signals respectively.

"Preferably, the drive control unit controls the initial enabled periods of the drive signals to be different from one another in response to the external control signal.

"Preferably, the drive control unit includes a first drive signal output unit corresponding to a first internal voltage generating unit generating a first internal voltage among the plurality of the internal voltage generating units and outputting a first drive signal for regulating the level of the first internal voltage by detecting a level of the first internal voltage by the external control signal; and a plurality of second drive signal output units corresponding to second internal voltage generating units generating second internal voltages among the plurality of the internal voltage generating units and outputting second drive signals having initial enabled periods different from one another by the external control signal and successive enabled periods according to the levels of the second internal voltages, respectively.

"Preferably, the respective second drive signal output unit includes an activating unit generating an activating signal in response to the external control signal; a detecting unit operating by the activation signal and detecting the level of the second internal voltage and outputting the detection result as a detection signal; an initial overdrive control unit generating an initial overdrive signal having a predetermined enabled period in response to the activation signal; and a drive signal generating unit generating the second drive signal by combining the detection signal and the initial overdrive signal.

"Preferably, the initial overdrive control unit generates the initial overdrive signal having the enabled period longer than the enabled period of the detection signal outputted at the initial operation of the detecting unit.

"Preferably, the drive signal generating unit generates the second drive signal which is enabled when at least one of the detection signal and the initial overdrive signal is in an enabled state.

"Preferably, the first drive signal output unit includes an activating unit generating an activation signal in response to the external control signal; and a detecting unit operating by the activation signal and detecting the level of the first internal voltage and outputting the detection result as a first drive signal.

"Preferably, the plurality of the internal voltage generating units include a first internal voltage generating unit generating the first internal voltage by driving the external voltage; and a second internal voltage generating unit generating the second internal voltage by pumping the external voltage.

"Preferably, the external control signal is an external command signal.

"According to a third embodiment of the present invention, there is provided a semiconductor device, which includes a first asynchronous internal voltage generating circuit generating a first internal voltage by varying the level of the an external voltage at a first point in a first drive manner in response to an external control signal; and a second asynchronous internal voltage generating circuit generating a second internal voltage by varying the level of the external voltage at a second point in a second drive manner in response to the external control signal.

"Preferably, the first asynchronous internal voltage generating circuit varies the level of the external voltage to the first internal voltage by driving the external voltage at the first point, and the second asynchronous internal voltage generating circuit varies the level of the external voltage to the second internal voltage by pumping the external voltage at the second point.

"Preferably, the first and second asynchronous internal voltage generating circuits vary the external voltage to the first and second internal voltage levels by pumping the external voltage at the first and second points, respectively.

"Preferably, the first asynchronous internal voltage generating circuit operates respectively in the first drive manner at a point that it operates firstly by the external control signal and a point that the level of the first internal voltage is varied, and the second asynchronous internal voltage generating circuit operates respectively in the second drive manner at a point that it operates firstly by the external control signal, a point between the point of the first operation and the point that the level of the first internal voltage is varied and a point that level of the second internal voltage is varied.

"Preferably, the second asynchronous internal voltage generating circuit includes an activating unit generating an activation signal determining a point of the first operation in response to the external control signal; a detecting unit operating in response to the activation signal and detecting the level of the second internal voltage and outputting a detection signal determining an operation point according to the level variation of the second internal voltage; an initial overdrive control unit generating an initial overdrive signal determining an operation point between the time point of the first operation and a point that the level of the first internal voltage is varied, in response to the activation signal; a drive signal generating unit generating a drive signal by combining the detection signal and the initial overdrive signal; and an internal voltage generating unit generating the second internal voltage by varying the level of the external voltage in the second drive manner in response to the drive signal.

"Preferably, the initial overdrive control unit generates the initial overdrive signal having a predetermined enabled period from a point of the enablement of the activation signal using the activation signal.

"Preferably, the initial overdrive signal has an enabled period which is longer than an enabled period of the detection signal outputted at the initial operation of the detecting unit.

"Preferably, the drive signal generating unit enables and outputs the drive signal when at least one of the detection signal and the initial overdrive signal is in an enabled state.

"Preferably, the first asynchronous internal voltage generating circuit includes an activating unit generating an activation signal determining a point of the initial operation in response to the external control signal; a detecting unit operating in response to the activation signal and detecting the level of the first internal voltage and outputting a detection signal determining an operation point according to the level variation of the first internal voltage; a driving unit driving the first internal voltage with the external voltage in response to the drive signal.

"Preferably, the external control signal corresponds to an external command signal.

"Preferably, the first internal voltage corresponds to a core voltage, and the second internal voltage corresponds to a pumping voltage."

For additional information on this patent, see: Han, Dong Hoon; Lee, Woo Young. Semiconductor Device Generating Varied Internal Voltages. U.S. Patent Number 8749299, filed September 8, 2008, and published online on June 10, 2014. Patent URL: http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=8749299.PN.&OS=PN/8749299RS=PN/8749299

Keywords for this news article include: Electronics, Hynix Semiconductor Inc..

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Source: Electronics Newsweekly


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