News Column

Patent Issued for Patterning Method

June 25, 2014



By a News Reporter-Staff News Editor at Electronics Newsweekly -- A patent by the inventors Hsu, Han-Hui (Hsinchu, TW); Hong, Shih-Ping (Hsinchu, TW); Wei, An-Chi (Hsinchu, TW); Wu, Ming-Tsung (Hsinchu, TW), filed on July 7, 2008, was published online on June 10, 2014, according to news reporting originating from Alexandria, Virginia, by VerticalNews correspondents.

Patent number 8748323 is assigned to MACRONIX International Co., Ltd. (Hsinchu, TW).

The following quote was obtained by the news editors from the background information supplied by the inventors: "The present invention relates to a semiconductor fabrication method, and more particularly to a patterning method.

"The demand for a higher resolution in a photolithography process goes up as dimensions of semiconductor devices continue to shrink. Generally, the resolution increases as the thickness of a photoresist layer decreases. The photoresist layer, however, must have a thickness sufficient to resist etching (i.e. anti-etching ability). Hence, the miniaturization of devices can hardly be achieved by reducing the thickness of the photoresist layer directly.

"Further, the incident light, which is through the photoresist layer and reflected from the substrate, interferes with a portion thereof, so as to cause a non-uniform exposure to the photoresist layer and result in a variation of critical dimensions. For example, the incident light and the reflected light combine in the photoresist layer to create standing waves and cause distortions in the patterns of the photoresist layer; thus, the undesired change of a line width, such as necking or bridging and even photoresist collapse occurs.

"Due to the above-mentioned problems, it is rather difficult when fabricating a metal line with a line width less than 80 nm. Therefore, the technology of enhancing the resolution without losing any anti-etching ability, and avoiding the reflection effect in the lithography process has been diligently pursued in the semiconductor industry."

In addition to the background information obtained for this patent, VerticalNews journalists also obtained the inventors' summary information for this patent: "The present invention provides a patterning method which can enhance the resolution without losing any anti-etching ability, and avoid the reflection effect in the lithography process, so as to fabricate a metal line with a line width less than 80 nm.

"The present invention provides a patterning method. First, a substrate having an objective material layer thereon is provided. Thereafter, a mask layer is formed on the objective material layer. Afterwards, a patterned layer is formed over the mask layer, wherein a material of the patterned layer concludes a metal-containing substance. Then, the mask is patterned to form a patterned mask layer. Further, the objective material layer is patterned, using the patterned mask layer as a mask.

"According to an embodiment of the present invention, the metal containing substance is selected from the group consisting of Ti, TiN, Ti/TiN, Ta, TaN, Ta/TaN, W, WN and W/WN.

"According to an embodiment of the present invention; an etch selectivity of the mask layer to the patterned layer is greater than about 3.

"According to an embodiment of the present invention, an etch selectivity of the mask layer to the patterned layer is greater than about 10.

"According to an embodiment of the present invention, an etch selectivity of the mask layer to the patterned layer is greater than about 15.

"According to an embodiment of the present invention, the method of forming the patterned layer includes the following steps. First, a stop layer is formed on the mask layer. Thereafter, a patterned photoresist layer is formed on the stop layer. Afterwards, the stop layer is etched, using the photoresist layer as a mask, to form the patterned layer. The patterned photoresist layer is then removed.

"According to an embodiment of the present invention, the step of forming the patterned layer further includes performing a trimming process to the patterned photoresist layer so as to reduce a line width before the step of etching the stop layer.

"According to an embodiment of the present invention, a material of the objective material layer comprises metal, polysilicon, polyside or metal salicide.

"According to an embodiment of the present invention, a material of the mask layer includes TEOS-SiO.sub.2, BPSG, PSG, HSQ, FSG, USG, SiN or SiON.

"According to an embodiment of the present invention, a thickness of the stop layer is between about 200 and 400 angstroms.

"According to an embodiment of the present invention, a thickness of the mask layer is between about 1000 and 4000 angstroms.

"The present invention also provides a patterning method. First, a stacking structure is provided on a substrate. The stacking structure includes an objective material layer, a dielectric material layer and at least a metal-containing substance layer subsequently formed on the substrate. Thereafter, the metal-containing substance layer is patterned to form the patterned layer. Afterwards, the dielectric material layer is etched by using the patterned layer as a mask to form a patterned dielectric layer. Then, the objective material layer is etched by using the patterned dielectric layer as a mask.

"According to an embodiment of the present invention, a material of the metal-containing substance layer is selected from the group consisting of Ti, TiN, Ti/TiN, Ta, TaN, Ta/TaN, W, WN and W/WN.

"According to an embodiment of the present invention, the method of forming the patterned layer includes the following steps. First, a patterned photoresist layer is formed on the stop layer. Thereafter, the metal-containing substance layer is etched, using the photoresist layer as a mask, to form the patterned layer. Afterwards, the patterned photoresist layer is removed.

"According to an embodiment of the present invention, the step of forming the patterned layer further includes performing a trimming process to the patterned photoresist layer so as to reduce a line width before the step of etching the metal-containing substance layer.

"According to an embodiment of the present invention, a material of the objective material layer includes Cu, AlCu or AlSiCu.

"The present invention further provides a patterning method. First, a substrate having a conductive layer thereon is provided. Thereafter, a mask layer is formed on the conductive layer. Afterwards, a patterned layer is formed over the mask layer. Then, an etching recipe is performed to pattern the mask layer, wherein an etch selectivity of the mask layer to the patterned layer is greater than 3. Further, the conductive layer is patterned, using the patterned mask layer as a mask.

"According to an embodiment of the present invention, the method of forming the patterned layer includes the following steps. First, a stop layer is formed on the mask layer. Thereafter, a patterned photoresist layer is formed on the stop layer. Afterwards, the stop layer is etched, using the photoresist layer as a mask, to form the patterned layer. The patterned photoresist layer is then removed.

"According to an embodiment of the present invention, the step of forming the patterned layer further includes performing a trimming process to the patterned photoresist layer so as to reduce a line width before the step of etching the stop layer.

"According to an embodiment of the present invention, a material of the mask layer includes TEOS-SiO.sub.2, BPSG, PSG, HSQ, FSG, USG, SiN or SiON.

"According to the patterning method of the present invention, a stop layer is disposed between the mask layer and the patterned photoresist layer to increase the resolution in a photolithography process as well as the anti-etching ability in an etching process. Therefore, the patterning method is beneficial for fabricating a line width less than 80 nm, and even for reducing critical dimensions of semiconductor devices.

"In order to make the aforementioned and other objects, features and advantages of the present invention comprehensible, a preferred embodiment accompanied with figures is described in detail below."

URL and more information on this patent, see: Hsu, Han-Hui; Hong, Shih-Ping; Wei, An-Chi; Wu, Ming-Tsung. Patterning Method. U.S. Patent Number 8748323, filed July 7, 2008, and published online on June 10, 2014. Patent URL: http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=8748323.PN.&OS=PN/8748323RS=PN/8748323

Keywords for this news article include: Electronics, Semiconductor, Photolithography, MACRONIX International Co. Ltd..

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Source: Electronics Newsweekly


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