News Column

Patent Application Titled "Self Evaluation of System on a Chip with Multiple Cores" Published Online

June 25, 2014



By a News Reporter-Staff News Editor at Electronics Newsweekly -- According to news reporting originating from Washington, D.C., by VerticalNews journalists, a patent application by the inventors Douskey, Steven M. (Rochester, MN); Fitch, Ryan A. (Southfield, MI); Hamilton, Michael J. (Rochester, MN); Kaufer, Amanda R. (Rochester, MN), filed on December 6, 2012, was made available online on June 12, 2014.

The assignee for this patent application is International Business Machines Corporation.

Reporters obtained the following quote from the background information supplied by the inventors: "This disclosure generally relates to testing and evaluation of electronic integrated circuits such as Application Specific Integrated Circuits (ASIC) and System-on-a-chip (SoC) designs, and more specifically relates to a method and apparatus for self evaluation of an integrated circuits such as an SoC or ASIC with multiple cores for Partial Good (PG) testing of the integrated circuit.

"Digital integrated circuits such as a system-on-a-chip (SoC) with ASIC or custom integrated circuit designs are becoming increasingly complex. SoC designs are including increasing numbers of microprocessor cores, some of which may be redundant for functional or manufacturing yield reasons. These multiple (microprocessor) cores are difficult to test and characterize as they are imbedded within the design. Multiple cores per die also increases manufacturing test time, complexity, and cost. As used herein, a 'core' is a microcontroller, processor, digital signal processor (DSP) or other large block of circuitry that is replicated with a number of instances on an integrated circuit.

"The testing of these devices is therefore becoming increasingly important. Testing of a device may be important at various stages, including in the design of the device, in the manufacturing of the device, and in the operation of the device. Testing during the manufacturing stage may be performed to ensure that the timing, proper operation and performance of the device are as expected. Ideally, it would be helpful to test the device for every possible defect. Because of the complexity of most devices, however, it is becoming prohibitively expensive to take the deterministic approach of testing every possible combination of inputs to each logic gate and states of the device. A more practical approach applies pseudorandom input test patterns to the inputs of the different logic gates. The outputs of the logic gates are then compared to the outputs generated by a 'good' device (one that is known to operate properly) in response to the same pseudorandom input test patterns. The more input patterns that are tested, the higher the probability that the logic circuit being tested operates properly (assuming there are no differences between the results generated by the two devices.)

"This non-deterministic approach can be implemented using built in test such as logic built-in self-test (LBIST) techniques. For example, one LBIST technique involves incorporating latches between portions of the logic being tested (the target logic,) loading these latches with pseudorandom bit patterns and then capturing the bit patterns that result from the propagation of the pseudorandom data through the target logic. Conventionally, the captured bit patterns are scanned out of the scan chains into a multiple-input signature register (MISR,) in which the bit patterns are combined with an existing signature value to produce a new signature value. This signature value can be examined (e.g., compared with the signature generated in a device that is known to operate properly) to determine whether or not the device under test functioned properly during the test.

"In some devices, such as multiprocessor integrated circuits and SoC, the device may be considered to be 'good,' even if some portions of the device include defects. For instance, in a SoC having multiple cores, the SoC may still be functional if one or more of the cores is defective. This is called Partial Good (PG) or PG testing."

In addition to obtaining background information on this patent application, VerticalNews editors also obtained the inventors' summary information for this patent application: "The disclosure and claims herein are directed to a method and structure to test a SoC or other integrated circuit having multiple cores for chip characterization or partial good status. A Self Evaluation Engine (SEE) on each core creates a quality metric or partial good value for the core. The SEE executes one or more tests to create a characterization signature for the core. The SEE then compares the characterization signature of a core with a characterization signature of neighboring cores to determine the partial good value for the core. The SEE may output a result to create a full characterization map for detailed diagnostics or a partial good map with values for all cores to produce a partial good status for the entire SoC.

"The foregoing and other features and advantages will be apparent from the following more particular description, as illustrated in the accompanying drawings.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWING(S)

"The disclosure will be described in conjunction with the appended drawings, where like designations denote like elements, and:

"FIG. 1 is a block diagram of an apparatus for testing multiple cores on a SoC;

"FIG. 2 illustrates a block diagram of a Signature Evaluation Engine (SEE) located in each core on a SoC;

"FIG. 3 illustrates a parallel compare for testing multiple cores on a SoC;

"FIG. 4 illustrates a serial compare for testing multiple cores on a SoC;

"FIG. 5 illustrates an example of core centric compare for testing multiple cores on a SoC;

"FIG. 6 illustrates a set of cores to illustrate an example for testing multiple cores on a SoC with the core centric compare in FIG. 5;

"FIG. 7 is a flow diagram for a method for testing multiple cores on a SoC; and

"FIG. 8 is a flow diagram for a method for implementing step 720 in the flow diagram of FIG. 7."

For more information, see this patent application: Douskey, Steven M.; Fitch, Ryan A.; Hamilton, Michael J.; Kaufer, Amanda R. Self Evaluation of System on a Chip with Multiple Cores. Filed December 6, 2012 and posted June 12, 2014. Patent URL: http://appft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&u=%2Fnetahtml%2FPTO%2Fsearch-adv.html&r=399&p=8&f=G&l=50&d=PG01&S1=20140605.PD.&OS=PD/20140605&RS=PD/20140605

Keywords for this news article include: Electronics, Microprocessors, International Business Machines Corporation.

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Source: Electronics Newsweekly


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