Patent Application Titled "Dynamic Reconfigurable Heterogeneous Processor Architecture with Load Balancing and Dynamic Allocation Method Thereof" Published Online
The assignee for this patent application is
Reporters obtained the following quote from the background information supplied by the inventors: "The present invention is a kind of computer architecture, a load balancing reconfigurable heterogeneous processor architecture with dynamic allocation method for high performance in particular.
"As today's semiconductor technology advances at a rate sketched by the Moore's law, the assorted digital information apparatus tends to integrate processors with various functions into SoC (System-on-a-Chip) to suit the needs of versatility and small form factor. While such an SoC is at work, the characteristics of the application tend to use some processors of certain type intensively but leave those of other types idling from time to time, causing the abundant hardware resources often unevenly used. This ever-changing needs for different types of processors along time greatly lower the overall performance.
"For example, the vastly used GPUs (Graphic Processing Units) in computer systems consist of large numbers of vertex shaders and pixel shaders. They process graphics through coordinate and light transformations, texture compression/decompression, bi-linear pixel shading, etc., to render graphics. The first task among these, vertex shading, shades vertices of geometries through coordinate and light transformation using a large number of vertex shaders. These shaded vertices are then passed on to another group of large number of pixel shaders and texture units for texture compression/decompression, bi-linear pixel shading, etc. As a result, often the number of pixels to be processed occasionally becomes much greater than the number of vertices, or while the vertex shaders are busy processing, the pixel shaders and texture units are idling; whereas while the pixel shaders and texture units are busy processing, the vertex shaders have little work to do. This fact makes the two sets of processors run unevenly along time, lowering the overall performance of the GPU. One solution may be to use unified shaders, but the costs are more complex shader circuits and routings.
"To deal with such a deficiency, the US Patent US2007/0091089A1 proposes a dynamically allocateable GPU system with method, which is equipped with multiple sharable units such as a sharable vertex processor, a sharable geometry processor, and a sharable pixel processor. Through at least one control unit, the sharable processors are assigned execution tasks, and the workload of each processor is monitored. Those unloaded sharable processors can be assigned to assist the loaded sharable processors.
"However, the aforementioned patent US2007/0091089A1 uses a plurality of shareable shaders to share the loads of various shading tasks, resulting in complicated hardware design and its associated monitoring and load sharing algorithm. The present invention is intended to resolve such difficulties. The present invention presents dynamic reconfigurable heterogeneous processors architecture with load balancing and dynamic allocation method"
In addition to obtaining background information on this patent application, VerticalNews editors also obtained the inventors' summary information for this patent application: "The primary objective of this invention is to propose a load-balancing, dynamic reconfigurable heterogeneous processors architecture with dynamic reconfiguration and allocation method. It uses a (plurality of) dynamically reconfigurable processor(s) to share the loads of heavily loaded processor(s) to improve overall system performance.
"A secondary objective of this invention is that it should achieve a good cost/performance measure. This is due to the increased performance is the result of only very small silicon area and energy overheads.
"A further objective of this invention is that it is easily applicable to the various digital system designs that process heterogeneous data and/or operations. The present invention's high compatibility with most such digital system designs is due to its efficient use of hardware and self-management.
"To achieve the aforementioned objectives, the presented invention, the dynamic reconfigurable heterogeneous processor architecture with load balancing and dynamic allocation method thereof, consists of a plurality of processors, one or more dynamic reconfigurable heterogeneous processors, and a work control logic unit. The dynamic reconfigurable heterogeneous processor(s) are treated similarly to the other processors, and the work control logic unit is connected to all these heterogeneous and reconfigurable processors. By monitoring the workload of each processor (possibly through examining the usage of its associated data buffer), the work control logic unit analyzes the loadings of all processors, and determines if which reconfigurable processor should be assigned to assist which processor type. Hence the goal of balancing processor workloads and increasing performance can be achieved.
"In the following, the embodiments of this invention are described in detail, together with schematic illustrations, to help understand the invention's objectives, its technical contents, special features, and how it achieves the goals.
BRIEF DESCRIPTION OF THE DRAWINGS
"FIG. 1 is a schematic diagram showing a dynamic reconfigurable heterogeneous processor system according to an embodiment of the present invention;
"FIG. 2 is a schematic diagram showing the system of a graphic processing unit according to an embodiment of the present invention;
"FIG. 3 is a flowchart of the load balancing dynamic allocation method according to an embodiment of the present invention;
"FIGS. 4(a)-4(d) are schematic diagrams showing operation requirement trees of a dynamic reconfigurable heterogeneous processor design according to an embodiment of the present invention;
"FIG. 5 is a schematic diagram showing block-selection trees of the dynamic reconfigurable heterogeneous processor design according to an embodiment of the present invention;
"FIG. 6 is a schematic diagram showing the block-selection trees of the dynamic reconfigurable heterogeneous processor design choosing the sharable operation nodes according to an embodiment of the present invention;
"FIG. 7 is a schematic diagram showing the block-selection trees of the dynamic reconfigurable heterogeneous processor design with multiplexer nodes added according to an embodiment of the present invention; and
"FIG. 8 is a schematic diagram showing the block-selection trees of the dynamic reconfigurable heterogeneous processor design choosing upward composable operation nodes and multiplexer nodes according to an embodiment of the present invention."
For more information, see this patent application: CHUNG, Chung-Ping; YANG, Hui-Chin; CHEN, Yi-Chi. Dynamic Reconfigurable Heterogeneous Processor Architecture with Load Balancing and Dynamic Allocation Method Thereof. Filed
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