News Column

New Circuits Research Findings Reported from University of Zielona

June 24, 2014

By a News Reporter-Staff News Editor at Journal of Technology -- Data detailed on Circuits Research have been presented. According to news reporting originating from Zielona Gora, Poland, by VerticalNews correspondents, research stated, "A new two-stage method of finite state machines (FSMs) synthesis for PAL-based complex programmable logic devices (CPLD) is proposed. It is based on both the wide fan-in of PAL cells and existence of the classes of pseudoequivalent states of Moore FSM."

Our news editors obtained a quote from the research from the University of Zielona, "The first step targets decreasing for the number of PAL cells used for implementing the block of input memory functions. The second step targets decreasing for the number of PAL cells in the block of microoperations."

According to the news editors, the research concluded: "An example of application of the proposed method is given, as well as results of experiments carried out for standard benchmarks."

For more information on this research see: Hardware Reduction In Cpld-based Moore Fsm. Journal of Circuits Systems and Computers, 2014;23(6):152-172. Journal of Circuits Systems and Computers can be contacted at: World Scientific Publ Co Pte Ltd, 5 Toh Tuck Link, Singapore 596224, Singapore.

The news editors report that additional information may be obtained by contacting A. Barkalov, Univ Zielona Gora, Inst Comp Engn & Elect, PL-65246 Zielona Gora, Poland. Additional authors for this research include L. Titarenko and S. Chmielewski.

Keywords for this news article include: Poland, Europe, Zielona Gora, Circuits Research

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Source: Journal of Technology

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