This patent application is assigned to
The following quote was obtained by the news editors from the background information supplied by the inventors: "The present invention relates to integrated chip capacitors, and more specifically, to capacitors using carbon nanotubes.
"Integrated chips generally include on-chip decoupling capacitors to suppress voltage spikes and other electrical disturbances from destroying the operative elements of the integrated chip. On-chip decoupling capacitors generally include a first electrode and a second electrode having a dielectric material formed in between. The capacitance is generally affected by the materials used, the surface area between the first electrode and second electrode and the distance between the electrodes. A common method of increasing capacitance includes increasing the surface area between the electrodes. In one method, a trench may be formed in the first electrode and the second electrode is formed into a prong that extends into the trench. Also, several of these trench/prong architectures may be linked to extend the surface area between the first and second electrodes."
In addition to the background information obtained for this patent application, VerticalNews journalists also obtained the inventors' summary information for this patent application: "According to one embodiment of the present invention, an on-chip decoupling capacitor includes: one or more carbon nanotubes coupled to a first electrode of the capacitor; a dielectric skin formed on the one or more carbon nanotubes; and a metal coating formed on the dielectric skin, wherein the dielectric skin is configured to electrically isolate the one or more carbon nanotubes from the metal coating.
"According to another embodiment of the present invention, an integrated chip includes: a first electrode; a second electrode; and a separation layer between the first electrode and the second electrode, wherein the separation layer is configured to include one or more carbon nanotubes having a dielectric skin on their surfaces.
"According to another embodiment of the present invention, an on-chip decoupling capacitor includes: a first electrode configured to form a plurality of trenches; a second electrode configured to form a plurality of prongs, wherein a selected prong of the second electrode is configured to extend into a selected trench of the first electrode; a separation layer between a first electrode and a second electrode, wherein the separating layer includes: a mesh of carbon nanotubes electrically coupled to the first electrode; a dielectric skin formed on the mesh of carbon nanotubes; and a metal coating formed on the dielectric skin.
"Additional features and advantages are realized through the techniques of the present invention. Other embodiments and aspects of the invention are described in detail herein and are considered a part of the claimed invention. For a better understanding of the invention with the advantages and the features, refer to the description and to the drawings.
BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS
"The subject matter which is regarded as the invention is particularly pointed out and distinctly claimed in the claims at the conclusion of the specification. The forgoing and other features, and advantages of the invention are apparent from the following detailed description taken in conjunction with the accompanying drawings in which:
"FIG. 1 shows an exemplary on-chip decoupling capacitor of the present invention that may be suitable for use in an integrated chip;
"FIG. 2 shows an exemplary configuration of carbon nanotubes used in forming the exemplary separation layer of the on-chip decoupling capacitor of FIG. 1;
"FIG. 3 shows a cross-sectional view of an exemplary separation layer of in FIG. 1;
"FIG. 4 shows a copper wire disposed in a trench formed in a bottom layer of interlayer dielectric material;
"FIG. 5 shows a bottom electrode formed on the copper wire and bottom dielectric layer of FIG. 4;
"FIG. 6 shows a separation layer deposited on the bottom electrode of FIG. 5;
"FIG. 7 shows a top electrode and a top metal deposited on the separation layer of FIG. 6;
"FIG. 8 shows an etched surface of a capacitive cell of the decoupling capacitor;
"FIG. 9 shows a second layer of interlayer dielectric material that is deposited on the top surface of the capacitive cell formed in FIG. 8;
"FIG. 10 shows a completed on-chip decoupling capacitor; and
"FIG. 11 shows a single decoupling capacitor that includes a plurality of trenches."
URL and more information on this patent application, see: Farmer, Damon B.;
Keywords for this news article include: Fullerenes, Nanotechnology, Carbon Nanotubes, Emerging Technologies,
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