News Column

"3d Rfics with Ultra-Thin Semiconductor Materials" in Patent Application Approval Process

June 25, 2014



By a News Reporter-Staff News Editor at Electronics Newsweekly -- A patent application by the inventors Han, Shu-Jen (Cortland Manor, NY); Valdes Garcia, Alberto (Hartsdale, NY), filed on December 5, 2012, was made available online on June 12, 2014, according to news reporting originating from Washington, D.C., by VerticalNews correspondents.

This patent application is assigned to International Business Machines Corporation.

The following quote was obtained by the news editors from the background information supplied by the inventors: "The present invention relates to three-dimensional integrated circuits and, more particularly, to three-dimensional radio-frequency integrated circuits using graphene-based components.

"Typical radio modules include an integrated circuit (IC) or set of ICs that perform radio frequency (RF)/analog functions, an antenna or antenna array, and a carrier board that integrates the components. Usually, the components are separate modules of are partially integrated in a package. This increases the overall form factor, cost, and complexity of the overall assembly process.

"Heterogeneous integration in one, two, or three dimensions is challenging if the verification and modeling tools are not integrated in the same platform. For example, modeling packaging separate from the ICs can result in frustrating mismatches and a lengthened design process.

"To address this, some RFICs are integrated with antennas in a three-dimensional chip. The antennas are formed a side of the RFIC opposite from the board connections to allow for proper propagation of the RF signals. However, it is difficult to integrate antennas on-chip, and the resulting RFIC can only have terminals on one side. This problem has been addressed in the past by providing through-silicon vias (TSVs), conductive channels that penetrate layers of the three-dimensional chip that allow connections between components. TSVs are not a perfect solution, however, because they cause high loss and have significant parasitics in the radio frequency domain. From a design point of view, TSVs have a large footprint compared to other components. Furthermore, vertical integration of modules with TSVs involves complex processes that are not compatible with standard circuit manufacturing techniques. As such, TSVs usually are not employed for antenna or other radio-frequency interconnects, complicating the design of three-dimensional RFICs."

In addition to the background information obtained for this patent application, VerticalNews journalists also obtained the inventors' summary information for this patent application: "A method for forming a three-dimensional integrated circuit is shown that includes forming one or more passive components in a passive-layer dielectric; depositing additional dielectric material on the passive-layer dielectric; forming a gate structure in the additional dielectric material; forming a gate dielectric layer on the gate structure and the additional dielectric material; forming a thin channel material on the gate dielectric; forming source and drain regions in electrical contact with the thin channel material to form a transistor; and passivating the transistor and providing electrical access to the source and drain regions.

"A method for forming a three-dimensional integrated circuit is shown that includes forming one or more surface components on a surface dielectric layer that is on a substrate; depositing a passive-layer dielectric material on the surface dielectric layer. forming one or more passive components in the passive-layer dielectric; depositing additional dielectric material on the passive-layer dielectric; forming a gate structure in the additional dielectric material; forming a gate dielectric layer on the gate structure and the additional dielectric material; forming a thin carbon-based channel material on the gate dielectric; forming source and drain regions in electrical contact with the thin channel material to form a transistor; passivating the transistor and providing electrical access to the source and drain regions; and etching the substrate to expose the one or more surface components.

"A three-dimensional integrated circuit is shown that includes an active layer comprising one or more active components formed with carbon-based channel material; a passive layer monolithically formed with the active layer, comprising one or more sub-layers, each sub-layer having one or more passive components, wherein the passive components have monolithically formed vertical interconnects to components on other layers; and a surface layer monolithically formed with the passive layer, comprising one or more surface components connected to one or more of the passive components through monolithically formed vias.

"These and other features and advantages will become apparent from the following detailed description of illustrative embodiments thereof, which is to be read in connection with the accompanying drawings.

BRIEF DESCRIPTION OF DRAWINGS

"The disclosure will provide details in the following description of preferred embodiments with reference to the following figures wherein:

"FIG. 1 is a cross-sectional view of a three-dimensional integrated circuit in accordance with the present principles;

"FIG. 2 is a cross-sectional view of a step of fabricating a three-dimensional integrated circuit in accordance with the present principles;

"FIG. 3 is a cross-sectional view of a step of fabricating a three-dimensional integrated circuit in accordance with the present principles;

"FIG. 4 is a cross-sectional view of a step of fabricating a three-dimensional integrated circuit in accordance with the present principles;

"FIG. 5 is a cross-sectional view of a step of fabricating a three-dimensional integrated circuit in accordance with the present principles;

"FIG. 6 is a cross-sectional view of a step of fabricating a three-dimensional integrated circuit in accordance with the present principles;

"FIG. 7 is a cross-sectional view of a step of fabricating a three-dimensional integrated circuit in accordance with the present principles;

"FIG. 8 is a cross-sectional view of a step of fabricating a three-dimensional integrated circuit in accordance with the present principles;

"FIG. 9 is a cross-sectional view of a step of fabricating a three-dimensional integrated circuit in accordance with the present principles;

"FIG. 10 is a cross-sectional view of a step of fabricating a three-dimensional integrated circuit in accordance with the present principles; and

"FIG. 11 is a block/flow diagram of fabricating a three-dimensional integrated circuit in accordance with one illustrative embodiment."

URL and more information on this patent application, see: Han, Shu-Jen; Valdes Garcia, Alberto. 3d Rfics with Ultra-Thin Semiconductor Materials. Filed December 5, 2012 and posted June 12, 2014. Patent URL: http://appft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&u=%2Fnetahtml%2FPTO%2Fsearch-adv.html&r=5831&p=117&f=G&l=50&d=PG01&S1=20140605.PD.&OS=PD/20140605&RS=PD/20140605

Keywords for this news article include: Electronics, Semiconductor, International Business Machines Corporation.

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Source: Electronics Newsweekly


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