News Column

Patent Application Titled "Electronic Component Embedded Substrate and Manufacturing Method Thereof" Published Online

June 27, 2014



By a News Reporter-Staff News Editor at Health & Medicine Week -- According to news reporting originating from Washington, D.C., by NewsRx journalists, a patent application by the inventors CHUNG, Yul Kyo (YONGIN, KR); LEE, DOO HWAN (DAEJEON, KR); LEE, SEUNG EUN (SUNGNAM, KR); SHIN, YEE NA (SUWON, KR), filed on November 26, 2013, was made available online on June 12, 2014 (see also Samsung Electro-mechanics Co., Ltd.).

The assignee for this patent application is Samsung Electro-mechanics Co., Ltd.

Reporters obtained the following quote from the background information supplied by the inventors: "The present invention relates to an electronic component embedded substrate.

"As the recently released mobile devices such as smartphones and tablet PCs have been dramatically improved in performance and demanded to have high portability, studies on miniaturization, slimming, and high performance of electronic components used in these mobile devices have been continuously conducted.

"Here, since an electronic component embedded substrate disclosed in Patent Document 1 etc. can secure a space for mounting extra components on its surface by embedding electronic components in a substrate, it has been highlighted as a way of implementing the miniaturization, slimming, and high performance of the electronic components mounted in the mobile devices.

"In particular, as the performance of semiconductor chips is improved, stability of power supplied to the semiconductor chips is considered as important. For this, a decoupling capacitor or a bypass capacitor is provided between the semiconductor chip and a power supply line to remove noise of power and supply a stable current to the semiconductor chip in a situation in which a power supply current is being changed suddenly.

"At this time, when mounting the semiconductor chip on the capacitor embedded substrate, since a distance between the decoupling capacitor and the semiconductor chip is minimized, it is possible to implement miniaturization and slimming while stably supplying power to the high performance semiconductor chip.

"Meanwhile, according to Patent Document 1, a method of fixing a capacitor after processing a cavity in a position where an electronic component is to be inserted, embedding the electronic component by thermocompression using an insulator, processing a micro via hole with laser, and achieving electrical connection through plating is disclosed.

"That is, in order to electrically connect between the electronic component embedded in a substrate and a circuit pattern provided on a surface of the substrate, a method of processing a via hole using laser and filling a conductive material in the via hole by a method such as plating has been commonly applied.

"According to this common method, minimum conditions on the area of a via contact which is to be formed in the embedded electronic component can be determined according to factors such as placing tolerance generated when the electronic component is embedded in the substrate, via hole processing tolerance, and via hole size.

"However, since the size of the via contact should be reduced according to a reduction in the size of the electronic component, as the electronic component becomes smaller, a matching error of the via and the electronic component is emerged as a serious problem."

In addition to obtaining background information on this patent application, NewsRx editors also obtained the inventors' summary information for this patent application: "The present invention has been invented in order to overcome the above-described problems and it is, therefore, an object of the present invention to provide an electronic component embedded substrate that can improve electrical connectivity of an electronic component embedded in a substrate.

"Further, it is another object of the present invention to provide a method of manufacturing an electronic component embedded substrate that can improve electronic connectivity of an electronic component embedded in a substrate.

"In accordance with one aspect of the present invention to achieve the object, there is provided an electronic component embedded substrate having an electronic component embedded therein, including: a cavity formed in at least one insulating layer provided inside the electronic component embedded substrate; an electronic component having at least a portion inserted in the cavity; and a cavity plating portion formed on a surface of the cavity opposite to at least one surface of the electronic component.

"At this time, an external electrode may be provided on a side surface of the electronic component, and the electronic component embedded substrate may further include a conductive filling portion formed by filling a conductive material between the cavity plating portion and the external electrode to electrically connect between the cavity plating portion and the external electrode.

"Further, the electronic component embedded substrate may further include a via having one surface in contact with at least one area selected from at least a portion of the external electrode, at least a portion of the conductive filling portion, and at least a portion of the cavity plating portion.

"Further, the external electrode may consist of at least two electrodes provided on a surface of the electronic component to be separated from each other, disconnecting portions may be formed in the cavity plating portion connected to the electrodes to electrically isolate the electrodes from each other, and a conductive filling portion may be filled between the respective cavity plating portions and the respective electrodes electrically separated by the disconnecting portions.

"Further, an insulating material may be filled in a space between the electrodes, between the disconnecting portions, and between the conductive filling portions.

"Further, the electronic component embedded substrate may further include a metal pattern provided on a surface of the insulating layer and electrically connected to the cavity plating portion and a via having one surface in contact with at least one area selected from at least a portion of the external electrode, at least a portion of the conductive filling portion, at least a portion of the cavity plating portion, and at least a portion of the metal pattern.

"At this time, the external electrode may consist of at least two electrodes provided on a surface of the electronic component to be separated from each other, disconnecting portions may be formed in the cavity plating portion connected to the electrodes to electrically isolate the electrodes from each other, and a conductive filling portion may be filled between the respective cavity plating portions and the respective electrodes electrically separated by the disconnecting portions.

"Further, an insulating material may be filled in a space between the electrodes, between the disconnecting portions, and between the conductive filling portions.

"Further, a plurality of electronic components may be inserted in the cavity, and at least two of the plurality of electronic components may be connected in parallel.

"Meanwhile, an external electrode may be provided on a side surface of the electronic component, and the cavity plating portion and the external electrode may be in contact with each other to be electrically connected to each other.

"In this case, the electronic component embedded substrate may further include a via having one surface in contact with at least one area selected from at least a portion of the external electrode and at least a portion of the cavity plating portion.

"Further, the external electrode may consist of at least two electrodes provided on a surface of the electronic component to be separated from each other, and disconnecting portions may be formed in the cavity plating portion connected to the electrodes to electrically isolate the electrodes from each other.

"Further, an insulating material may be filled in a space between the electrodes and between the disconnecting portions.

"Further, the electronic component embedded substrate may further include a metal pattern provided on a surface of the insulating layer and electrically connected to the cavity plating portion and a via having one surface in contact with at least one area selected from at least a portion of the external electrode, at least a portion of the cavity plating portion, and at least a portion of the metal pattern.

"At this time, the external electrode may consist of at least two electrodes provided on a surface of the electronic component to be separated from each other, and disconnecting portions may be formed in the cavity plating portion connected to the electrodes to electrically isolate the electrodes from each other.

"Further, an insulating material may be filled in a space between the electrodes and between the disconnecting portions.

"In accordance with another aspect of the present invention to achieve the object, there is provided an electronic component embedded substrate in which an electronic component including a hexahedral body portion and two external electrodes which cover opposite surfaces of the body portion is embedded, including: a cavity formed in at least one insulating layer provided inside the electronic component embedded substrate; and a cavity plating portion formed on a surface of the cavity opposite to the external electrode.

"In accordance with another aspect of the present invention to achieve the object, there is provided an electronic component embedded substrate including: a first insulating layer having a first metal pattern on a lower surface and a second metal pattern on an upper surface and including a cavity passing through the upper surface and the lower surface; an electronic component having at least one external electrode on a surface and having at least a portion inserted in the cavity; a cavity plating portion formed on a surface of the cavity opposite to the external electrode to be electrically connected to at least one of the first metal pattern and the second metal pattern; a conductive filling portion formed by filling a conductive material between the cavity plating portion and the external electrode; a second insulating layer for covering exposed surfaces of the first metal pattern, the first insulating layer, the cavity plating portion, the conductive filling portion, and the electronic component; a first circuit pattern formed on a surface of the second insulating layer; and a via having one surface in contact with at least one area selected from at least a portion of the external electrode, at least a portion of the conductive filling portion, at least a portion of the cavity plating portion, and at least a portion of the first metal pattern portion in contact with the cavity plating portion, and the other surface in contact with the first circuit pattern.

"At this time, the electronic component may have at least two external electrodes formed in separated areas on a surface of the electronic component, disconnecting portions may be formed in the cavity plating portion connected to the external electrodes to electrically isolate the electrodes from each other, and the conductive filling portion may be filled between the respective cavity plating portions and the respective external electrodes electrically separated by the disconnecting portions.

"Further, a material of the second insulating layer may be filled in a space between the external electrodes, between the disconnecting portions, and between the conductive filling portions.

"Further, the electronic component embedded substrate may further include a fifth via having one surface in contact with at least a portion of the first metal pattern except the portion in contact with the cavity plating portion, and the other surface in contact with at least a portion of the first circuit pattern.

"Further, the electronic component embedded substrate may further include a third insulating layer for covering the exposed surfaces of the first insulating layer, the cavity plating portion, the conductive filling portion, and the electronic component; a second circuit pattern formed on a surface of the third insulating layer; and a third via having one surface in contact with at least one area selected from at least a portion of the external electrode, at least a portion of the conductive filling portion, at least a portion of the cavity plating portion, and at least a portion of the second metal pattern portion in contact with the cavity plating portion, and the other surface in contact with the second circuit pattern.

"At this time, at least one of a material of the first insulating layer and a material of the second insulating layer may be filled in a space between the external electrodes, between the disconnecting portions, and between the conductive filling portions.

"Further, the electronic component embedded substrate may further include a sixth via having one surface in contact with at least a portion of the second metal pattern except the portion in contact with the cavity plating portion, and the other surface in contact with at least a portion of the second circuit pattern.

"In accordance with another aspect of the present invention to achieve the object, there is provided a method of manufacturing an electronic component embedded substrate having an electronic component embedded therein, including the steps of: (A) forming a cavity in at least one insulating layer provided inside the electronic component embedded substrate and forming a cavity plating portion by plating a conductive material on a surface of the cavity; and (B) inserting at least a portion of the electronic component in the cavity.

"At this time, the method of manufacturing an electronic component embedded substrate may further include the step of filling a conductive material in a space between the electronic component and the cavity plating portion after the step (B).

"Further, the step (A) may include the steps of: (A1) forming a temporary remaining portion in a portion of the area in which the cavity is to be formed by processing a first temporary cavity having a '.OR right.' shape and a second temporary cavity having a shape symmetrical to the first temporary cavity to face each other while being separated from each other by a predetermined interval; (A2) plating a conductive material on surfaces of the first temporary cavity and the second temporary cavity; and (A3) removing the temporary remaining portion.

"Further, the step (A) may include the steps of: (a1) forming a third temporary cavity in an area except a first projecting portion formed by projecting the insulating layer in the direction of a surface facing one surface of the cavity and a second projecting portion formed to be symmetrical to the first projecting portion on a surface facing the surface on which the first projecting portion is formed; (a2) plating a conductive material on a surface of the third temporary cavity; and (a3) removing portions of the first projecting portion and the second projecting portion.

"In accordance with another aspect of the present invention to achieve the object, there is provided a method of manufacturing an electronic component embedded substrate, including the steps of: (a) providing a first insulating layer having a first metal pattern on a lower surface and a second metal pattern on an upper surface; (b) forming a cavity in the first insulating layer and forming a cavity plating portion electrically connected to at least one of the first metal pattern and the second metal pattern by plating a conductive material on a surface of the cavity; attaching a detach film to a lower surface of the first metal pattern; (d) attaching a lower surface of an electronic component to the detach film by inserting at least a portion of the electronic component having a plurality of external electrodes on a surface; (e) forming a conductive filling portion by filling a conductive material between the cavity plating portion and the external electrodes; (f) forming a third insulating layer by applying an insulating material on exposed surfaces of the second metal pattern, the first insulating layer, the cavity plating portion, the conductive filling portion, and the electronic component; (g) processing a via hole, which exposes at least one area selected from at least a portion of the external electrodes, at least a portion of the conductive filling portion, at least a portion of the cavity plating portion, and at least a portion of the second metal pattern portion in contact with the cavity plating portion, through the third insulating layer; and (h) filling a conductive material in the via hole and forming a second circuit pattern on an upper surface of the third insulating layer.

"At this time, the step (b) may include the steps of: (b1) forming a temporary remaining portion in a portion of the area in which the cavity is to be formed by processing a first temporary cavity having a '.OR right.' shape and a second temporary cavity having a shape symmetrical to the first temporary cavity to face each other while being separated from each other by a predetermined interval; (b2) plating a conductive material on surfaces of the first temporary cavity and the second temporary cavity; and (b3) removing the temporary remaining portion.

"Further, the step (b) may include the steps of: (b1') forming a third temporary cavity in an area except a first projecting portion formed by projecting the insulating layer in the direction of a surface facing one surface of the cavity and a second projecting portion formed to be symmetrical to the first projecting portion on a surface facing the surface on which the first projecting portion is formed; (b2') plating a conductive material on a surface of the third temporary cavity; and (b3') removing portions of the first projecting portion and the second projecting portion.

"In accordance with another aspect of the present invention to achieve the object, there is provided a method of manufacturing an electronic component embedded substrate, including the steps of: (f1) forming a third insulating layer by applying an insulating material on exposed surfaces of a second metal pattern, a first insulating layer, a cavity plating portion, a conductive filling portion, and an electronic component; (f2) forming a second insulating layer by applying an insulating material on the exposed surfaces of a first metal pattern, the first insulating layer, the cavity plating portion, the conductive filling portion, and the electronic component after removing a detach film; (g1) forming a first via passing through the second insulating layer and a first circuit pattern provided on a lower surface of the second insulating layer to be connected to the first via; and (g2) forming a third via passing through the third insulating layer and a second circuit pattern provided on an upper surface of the third insulating layer to be connected to the third via, wherein one surface of the first via is in contact with at least one area selected from at least a portion of external electrodes, at least a portion of the conductive filling portion, at least a portion of the cavity plating portion, and at least a portion of the first metal pattern portion in contact with the cavity plating portion, and one surface of the third via is in contact with at least one area selected from at least a portion of the external electrodes, at least a portion of the conductive filling portion, at least a portion of the cavity plating portion, and at least a portion of the second metal pattern portion in contact with the cavity plating portion.

"At this time, the step (d) may be performed to attach the lower surface of the electronic component to the detach film by inserting a plurality of electronic components in the cavity.

"Further, at least two of the plurality of electronic components may be connected in parallel.

BRIEF DESCRIPTION OF THE DRAWINGS

"These and/or other aspects and advantages of the present general inventive concept will become apparent and more readily appreciated from the following description of the embodiments, taken in conjunction with the accompanying drawings of which:

"FIG. 1 is a cross-sectional view schematically showing an electronic component embedded substrate in accordance with an embodiment of the present invention;

"FIG. 2 is a plan view showing the surface taken along line I-I' of FIG. 1 in the electronic component embedded substrate in accordance with an embodiment of the present invention;

"FIG. 3 is a plan view showing the surface taken along line I-I' of FIG. 1 in an electronic component embedded substrate in accordance with another embodiment of the present invention;

"FIG. 4 is a plan view showing the surface taken along line I-I' of FIG. 1 in an electronic component embedded substrate in accordance with still another embodiment of the present invention;

"FIGS. 5a to 5i are process diagrams schematically showing a method of manufacturing an electronic component embedded substrate in accordance with an embodiment of the present invention, wherein

"FIG. 5a is a cross-sectional view schematically showing the state in which a first metal pattern and a second metal pattern are formed on a first insulating layer,

"FIG. 5b is a cross-sectional view schematically showing the state in which a cavity is formed in the first insulating layer,

"FIG. 5c is a cross-sectional view schematically showing the state in which a cavity plating portion is formed in the cavity,

"FIG. 5d is a cross-sectional view schematically showing the state in which a detach film is attached to the first metal pattern,

"FIG. 5e is a cross-sectional view schematically showing the state in which an electronic component is inserted in the cavity,

"FIG. 5f is a cross-sectional view schematically showing the state in which a conductive filling portion is formed,

"FIG. 5g is a cross-sectional view schematically showing the state in which a third insulating layer is formed,

"FIG. 5h is a cross-sectional view schematically showing the state in which a second insulating layer is formed, and

"FIG. 5i is a cross-sectional view schematically showing the state in which first to sixth vias, a first circuit pattern, and a second circuit pattern are formed;

"FIGS. 6a to 6d are process diagrams schematically showing the process of forming the cavity having the cavity plating portion in the first insulating layer in the method of manufacturing an electronic component embedded substrate in accordance with an embodiment of the present invention, wherein

"FIG. 6a is a plan view schematically showing the state in which a first temporary cavity and a second temporary cavity are formed,

"FIG. 6b is a plan view schematically showing the state in which a resist portion is formed,

"FIG. 6c is a plan view schematically showing the state in which a plating process is performed, and

"FIG. 6d is a plan view schematically showing the state in which a temporary remaining portion and the resist portion are removed; and

"FIGS. 7a to 7c are process diagrams schematically showing a process of forming a cavity having a cavity plating portion in a first insulating layer, wherein

"FIG. 7a is a plan view schematically showing the state in which a first projecting portion and a second projecting portion are formed,

"FIG. 7b is a plan view schematically showing the state in which a plating process is performed, and

"FIG. 7c is a plan view schematically showing the state in which the first projecting portion and the second projecting portion are removed."

For more information, see this patent application: CHUNG, Yul Kyo; LEE, DOO HWAN; LEE, SEUNG EUN; SHIN, YEE NA. Electronic Component Embedded Substrate and Manufacturing Method Thereof. Filed November 26, 2013 and posted June 12, 2014. Patent URL: http://appft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&u=%2Fnetahtml%2FPTO%2Fsearch-adv.html&r=6368&p=128&f=G&l=50&d=PG01&S1=20140605.PD.&OS=PD/20140605&RS=PD/20140605

Keywords for this news article include: Semiconductor, Microtechnology, Electronic Components, Samsung Electro-mechanics Co. Ltd..

Our reports deliver fact-based news of research and discoveries from around the world. Copyright 2014, NewsRx LLC


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Source: Health & Medicine Week


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