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Researchers Submit Patent Application, "Network Processor Unit and a Method for a Network Processor Unit", for Approval

June 18, 2014



By a News Reporter-Staff News Editor at Electronics Newsweekly -- From Washington, D.C., VerticalNews journalists report that a patent application by the inventors NORDMARK, Gunnar (Stockholm, SE); BODEN, Thomas (Strangnas, SE); CARLSTROM, Jakob (Uppsala, SE); SUKONIK, Vitaly (Katzir, IL); PERSSON, Mattias (Bromma, SE), filed on January 7, 2014, was made available online on June 5, 2014.

The patent's assignee is Marvell International Ltd.

News editors obtained the following quote from the background information supplied by the inventors: "A network processor may be used as a single-chip switch/router or on an ingress or egress line card in a modular switch/router. Many prior art network processors comprise several intermediate buffers that are used between different modules of the network processor, causing the network processor to have more buffer space than needed. Further, the several intermediate buffers may cause latency during processing.

"FIG. 1 schematically shows a prior art network processor 1 having several intermediate buffers. As illustrated, the network processor 1 comprises a traffic manager 2, interfaces 3, buffers 4a, 4b, 4c, with queues and schedulers, processing means 5, and optional external memories 6a, 6b, cf. FIG. 1. Packet data received from the interfaces 3 are buffered in an input buffer 4a, processed by the processing means 5, buffered in an intermediate buffer 4b before being written to the buffers of the traffic manager 2. From the traffic manager 2, the packet data is scheduled and transmitted on the interfaces 3 via an output buffer 4c. Due to varying requirements between different systems, the ideal sequence of packet processing varies. For example, all or part of the traffic leaving the traffic manager may require an additional pass through the processing means before transmission as illustrated by a loopback path 7. In other cases, two passes through the traffic manager may be required.

"A drawback with the prior art network processor 1 is the large required buffer size, which is larger than needed. If for example, a burst of packet data passes through the network processor 1 of FIG. 1, it is first stored in the input buffer 4a, later in the intermediate buffer 4b and last in the output buffer 4c. This means that each of the buffers; input buffer, the intermediate buffer and the output buffer, must provide buffer space for a normal amount of packet data and for the burst size.

"Another drawback with the prior art network processor is the sequential flow of packets through the network processor. As illustrated in FIG. 1, firstly, the packets are received on the interface; secondly, they are buffered in the input buffer; thirdly, they are processed by the processing means; fourthly, they are buffered in the intermediate buffer; fifthly, they are written to the buffers of the traffic manager; and sixthly, they are buffered in an output buffer; and seventhly, they arc transmitted on the interfaces.

"U.S. 2005/0169259 to Su et al discloses a packet switching unit comprising ports, a packet switching control unit, a microprocessor data transfer interface, a microprocessor, and a packet buffer. The packet buffer comprises a packet area, an index buffer and a transfer queue circuitry. Both the packet switching control unit and the microprocessor data transfer interface can transfer packet from/to the ports and the microprocessor, respectively.

"A drawback with the packet switching unit to Su et al is that it also requires large buffer space, since the ports have a store-and-forward functionality implying that the packets are stored by the ports before they are moved into the packet buffer.

"U.S. 2007/0230475 to Langner discloses a switch-based network processor comprising input interfaces, output interfaces, processing elements, and a switch with bidirectional ports. The network processor associates information with a packet received via an input interface, and this information is sequentially processed through multiple ones of the processing elements in serial order based on switching operations of the switch. The network processor may be viewed as providing selectable interconnection between inputs and outputs of the various processing elements dependent on the application. For a certain application, packets will therefore flow only to the particular processing elements that are needed and in the appropriate order. The sequence of processing elements is obtained by configuration of the switch and of the processing elements.

"A drawback with the network processor to Langner is the predetermined serial order of packet switching for a given application such as a secure transaction server application, a secure sockets layer (SSL) VPN firewall application or a secure Internet protocol (IPSEC) VPN firewall application. After configuration for a specific application, all packets will have the same serial processing order and thus will take the same path through the network processor."

As a supplement to the background information on this patent application, VerticalNews correspondents also obtained the inventors' summary information for this patent application: "It's an aim of the present invention to overcome the drawbacks and disadvantages of the prior art. More specifically, it is an aim of the present invention to minimize the size of the buffers in a network processor and to provide flexible paths for packets through the network processor in order to adapt to differing system requirements.

"The above mentioned aim among others is fulfilled with a method and a network processor unit according to the independent claims. Further embodiments of the invention are specified in the dependent claims.

DETAILED DESCRIPTION OF DRAWINGS

"Embodiments of the present invention will be described in more detail with reference to the following drawings, in which:

"FIG. 1 schematically illustrates a block diagram of a prior art network processor;

"FIG. 2 schematically illustrates a block diagram of a network processor according to an embodiment of the present invention;

"FIG. 3 schematically illustrates a block diagram of a network processor according to an embodiment of the present invention;

"FIG. 4a schematically illustrates a block diagram of an embodiment of a network processor according to the present invention;

"FIG. 4b schematically illustrates a block diagram of an embodiment of a network processor according to the present invention;

"FIG. 5a schematically illustrates block diagram of an embodiment of a network processor according to the present invention, wherein a scheduling view of an embedded switch is shown, and

"FIG. 5b schematically illustrates block diagram of an embodiment of a network processor according to the present invention, wherein a scheduling view of an embedded switch is shown."

For additional information on this patent application, see: NORDMARK, Gunnar; BODEN, Thomas; CARLSTROM, Jakob; SUKONIK, Vitaly; PERSSON, Mattias. Network Processor Unit and a Method for a Network Processor Unit. Filed January 7, 2014 and posted June 5, 2014. Patent URL: http://appft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&u=%2Fnetahtml%2FPTO%2Fsearch-adv.html&r=3326&p=67&f=G&l=50&d=PG01&S1=20140529.PD.&OS=PD/20140529&RS=PD/20140529

Keywords for this news article include: Electronics, Microprocessors, Packet Switching, Marvell International Ltd..

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Source: Electronics Newsweekly


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