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Researchers Submit Patent Application, "Memory Systems Including Flash Memories, First Buffer Memories, Second Buffer Memories and Memory Controllers...

June 18, 2014



Researchers Submit Patent Application, "Memory Systems Including Flash Memories, First Buffer Memories, Second Buffer Memories and Memory Controllers and Methods for Operating the Same", for Approval

By a News Reporter-Staff News Editor at Electronics Newsweekly -- From Washington, D.C., VerticalNews journalists report that a patent application by the inventor IM, Kwangseok (Seoul, KR), filed on November 25, 2013, was made available online on June 5, 2014.

The patent's assignee is Samsung Electronics Co., Ltd.

News editors obtained the following quote from the background information supplied by the inventors: "The inventive concepts described herein relate to flash memory devices, and more particularly, to flash memory based memory systems and/or operating methods thereof.

"A flash memory device may be one type of nonvolatile memory device. The flash memory device may provide a data access speed which is higher than a data access speed of a conventional hard disk drive. Also, size and power consumption of the flash memory device may be less than those of the conventional hard disk drive. Since the flash memory device is tolerant of external shocks, it may be widely used as a storage device for a portable device.

"Also, since an operating speed of the flash memory device is slower than that of a central processing unit (CPU), a buffer memory may be used to compensate for a speed difference between the flash memory device and the CPU. In recent years, as interfaces for flash memory devices, memory controllers, and hosts have developed, improvement on the performance of such buffer memories may be required. In case of a dynamic random-access memory (DRAM) being used as a buffer memory, a flash memory based storage device may not perform optimally."

As a supplement to the background information on this patent application, VerticalNews correspondents also obtained the inventor's summary information for this patent application: "One example embodiment of the inventive concepts is directed to provide an operating method of a memory system including a flash memory, a first buffer memory, a second buffer memory and a memory controller. The operating method includes reading data stored at the flash memory and generating an address corresponding to a region of the first buffer memory at which the read data is to be stored. The operating method further includes determining whether the second buffer memory is at an erase state and if the determining indicates that the second buffer memory is at an erase state, storing the read data at the second buffer memory and the generated address of the first buffer memory at an internal register.

"In yet another example embodiment, the operating method further includes, if the determining indicates that the second buffer memory is not at an erase state, storing the read data at a region of the first buffer memory corresponding to the stored address of the first buffer memory.

"In yet another example embodiment, the operating method further includes receiving a read address from a host, comparing the read address and the stored address of the first buffer memory and transferring data corresponding to the read address to the host according to the comparing.

"In yet another example embodiment, the transferring includes transferring data stored at the second buffer memory to the host, if the stored address of the first buffer memory is equal to the read address.

"In yet another example embodiment, the transferring includes transferring data of the first buffer memory corresponding to the read address to the host, if the stored address of the first buffer memory is not equal to the read address.

"In yet another example embodiment, if the second buffer memory is not accessed during a period of time, the method further includes flushing data stored at the second buffer memory to a region of the first buffer memory corresponding to the stored address of the first buffer memory.

"In yet another example embodiment, an operating speed of the second buffer memory is higher than an operating speed of the first buffer memory.

"In yet another example embodiment, the operating method further includes generating selection information indicating that the second buffer memory is at one of an erase state and a program state based on the determining.

"In one example embodiment of the inventive concepts, a memory system includes a flash memory; a first buffer memory; and a memory controller configured to generate an address of the first buffer memory at which data read from the flash memory is to be stored. The memory controller includes a second buffer memory and a buffer manager. The memory controller is configured to generate selection information indicating whether the second buffer memory is at one of an erase state and a program state. The buffer manager is further configured to store the read data at one of the first buffer memory and the second buffer memory based on the selection information and store the generated address of the first buffer memory based on the selection information.

"In yet another example embodiment, the memory controller is further configured to flush the data stored at the second buffer memory to a region of the first buffer memory corresponding to the stored address of the first buffer memory, when the second buffer memory is not accessed during a period of time.

"In yet another example embodiment, the buffer manager includes a de-multiplexer configured to receive the generated address of the first buffer memory, the read data and the selection information. The de-multiplexer is further configured to select one of the first buffer memory and the second buffer memory based on at least the selection information. The buffer manager further includes a register configured to selectively store the address of the first buffer memory based on the selection information and a comparator configured to compare the address stored at the register with the read address. The buffer manager further includes a multiplexer configured to transfer data stored at the selected one of the first buffer memory and the second buffer memory to the host based on an output of the comparator.

"In yet another example embodiment, the first buffer memory and the second buffer memory are formed of different types of random access memories.

"In yet another example embodiment, an operating speed of the second buffer memory is higher than an operating speed of the first buffer memory.

"In yet another example embodiment, the flash memory and the memory controller are connected via a plurality of channels and each of the first buffer memory and the second buffer memory includes a plurality of buffer memory units, each of the plurality of buffer memory units corresponding to one of the plurality of channels.

"In yet another example embodiment, the memory controller is connected with a host based on a peripheral component interconnection-express (PCI-E) based interface.

"In one example embodiment, a method includes determining, for a memory system comprising a first buffer memory and a second buffer memory, a state of the second buffer memory and designating at least one of the first buffer memory and the second buffer memory for storing data based on the determined state of the second buffer memory.

"In yet another example embodiment, the method further includes receiving a read data request from a host and reading data corresponding to the received read data request from a flash memory.

"In yet another example embodiment, the method further includes generating an address at the first buffer memory for storing the read data.

"In yet another example embodiment, the determining the state of the second buffer memory includes generating selecting information indicating whether the second buffer memory is at an erase state

"In yet another example embodiment, the determining determines that the second buffer memory is at the erase state if the generated selection information is a logical 1.

"In yet another example embodiment, the designating designates the second buffer memory for storing the read data, if the generated selection information indicates that the second buffer memory is at the erase state.

"In yet another example embodiment, upon designating the second buffer memory for storing the read data, the method further includes determining an amount of time since the host last accessed the second buffer memory and flushing the data stored in the second buffer memory to a region of the first buffer memory corresponding to the generated address of the first buffer memory.

"In yet another example embodiment, the method further includes receiving the generated address of the first buffer memory, the read data and the generated selection information and selecting at least one of the first buffer memory and the second buffer memory based on at least the generated selection information. The method further includes selectively storing, at a register, the address of the first buffer memory based on the generated selection information, comparing the selectively stored address with an address associated with the read data and transferring data stored at the selected one of the first buffer memory and the second buffer memory, to the host based on the comparing.

"In yet another example embodiment, the first buffer memory and the second buffer memory are formed of different types of random access memories.

"In yet another example embodiment, an operating speed of the second buffer memory is higher than an operating speed of the first buffer memory.

BRIEF DESCRIPTION OF THE DRAWINGS

"The above and other objects and features will become apparent from the following description with reference to the following figures, wherein like reference numerals refer to like parts throughout the various figures unless otherwise specified, and wherein

"FIG. 1 is a block diagram schematically illustrating a computing system based on a flash memory, according to an example embodiment of the inventive concepts;

"FIG. 2 is a flowchart schematically illustrating an operating method of a memory controller in FIG. 1, according to an example embodiment;

"FIG. 3 is a diagram schematically illustrating a physical structure of first and second buffer memories in FIG. 1, according to an example embodiment;

"FIGS. 4A and 4B are diagrams for describing an operating method of a memory controller in FIG. 1, according to an example embodiment;

"FIGS. 5A and 5B are diagrams for describing an operating method of a memory controller, according to an example embodiment of the inventive concepts;

"FIG. 6 is a block diagram schematically illustrating first and second buffer memories and a buffer manager, according to an example embodiment of the inventive concepts;

"FIG. 7 is a block diagram schematically illustrating a buffer manager corresponding to a plurality of channels, according to an example embodiment of the inventive concepts; and

"FIG. 8 is a block diagram schematically illustrating storage, according to an example embodiment of the inventive concepts."

For additional information on this patent application, see: IM, Kwangseok. Memory Systems Including Flash Memories, First Buffer Memories, Second Buffer Memories and Memory Controllers and Methods for Operating the Same. Filed November 25, 2013 and posted June 5, 2014. Patent URL: http://appft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&u=%2Fnetahtml%2FPTO%2Fsearch-adv.html&r=508&p=11&f=G&l=50&d=PG01&S1=20140529.PD.&OS=PD/20140529&RS=PD/20140529

Keywords for this news article include: Samsung Electronics Co. Ltd.

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Source: Electronics Newsweekly


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