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Researchers Submit Patent Application, "Integrated Junction and Junctionless Nanotransistors", for Approval

June 18, 2014



By a News Reporter-Staff News Editor at Electronics Newsweekly -- From Washington, D.C., VerticalNews journalists report that a patent application by the inventors Suk, Sung-Dae (Seoul, KR); Oh, Changwoo (Suwon-si, KR); Park, Sungil (Suwon-si, KR), filed on November 25, 2013, was made available online on June 5, 2014.

No assignee for this patent application has been made.

News editors obtained the following quote from the background information supplied by the inventors: "Example embodiments of the inventive concepts relate to semiconductor devices, and in particular, to semiconductor devices with transistors whose threshold voltages are different from each other.

"Semiconductor integrated circuit devices are increasingly being used in consumer, commercial and other electronic devices. The semiconductor devices can include a memory device for storing data, a logic device for processing data, and a hybrid device including both of memory and logic elements. Due to the increased demand for electronic devices with fast speed and/or low power consumption, the semiconductor devices should provide a fast operating speed and/or a low operating voltage. To satisfy these technical requirements, the complexity and/or increased integration density of semiconductor devices may increase."

As a supplement to the background information on this patent application, VerticalNews correspondents also obtained the inventors' summary information for this patent application: "Example embodiments of the inventive concepts can provide a semiconductor device with transistors whose threshold voltages are different from each other.

"According to example embodiments of the inventive concepts, a semiconductor device includes a first transistor and a second transistor integrated on a substrate, each of the first and second transistors including a nano-sized active region including source and drain regions in respective end portions of the nano-sized active region and a channel forming region between the source and drain regions. The source and drain regions of the first transistor have the same conductivity type as those of the second transistor, the second transistor has a threshold voltage lower than that of the first transistor, and the channel forming region of the second transistor may include a homogeneously doped region, whose conductivity type may be the same as the source and drain regions of the second transistor and may be different from the channel forming region of the first transistor.

"In example embodiments, during an operation of the semiconductor device, carriers having the same conductivity type as minority carriers of the source and drain regions of the second transistor may be accumulated in the homogeneously doped region of the second transistor to form an inversion region.

"In example embodiments, the second transistor may be turned off due to the presence of the inversion region.

"In example embodiments, a depth of the inversion region from a surface of the nano-sized active region protruding from the substrate may be substantially the same as those of the source and drain regions of the second transistor.

"In example embodiments, a doping concentration of the homogeneously doped region may be lower than those of the source and drain regions of the second transistor.

"In example embodiments, the doping concentration of the homogeneously doped region decreases with increasing distance from the source and drain regions of the second transistor.

"In example embodiments, the homogeneously doped region connects the source and drain regions of the second transistor to each other.

"In example embodiments, the device may further include a third transistor including source and drain regions, whose conductivity type may be the same as those of the source and drain regions of the first transistor, and a channel forming region between the source and drain regions. The channel forming region of the third transistor may include a first homogeneously doped region connected to the source region of the third transistor, a second homogeneously doped region connected to the drain region of the third transistor, and a heterogeneously doped region connecting the first homogeneously doped region with the second homogeneously doped region. The first and second homogeneously doped regions have the same conductivity type as the source and drain regions of the third transistor, and the heterogeneously doped region has a different conductivity type from the source and drain regions of the third transistor.

"In example embodiments, a threshold voltage of the third transistor may be lower than that of the first transistor and higher than that of the second transistor.

"In example embodiments, the threshold voltage of the third transistor decreases with decreasing width of the heterogeneously doped region and increases with increasing width of the heterogeneously doped region.

"In example embodiments, a doping concentration of the first homogeneously doped region decreases with increasing distance from the source region of the third transistor, and a doping concentration of the second homogeneously doped region decreases with increasing distance from the drain region of the third transistor.

"In example embodiments, during an operation of the semiconductor device, the third transistor may be turned-off by an inversion region to be formed in the first and second homogeneously doped regions and may be turned-on by an inversion region in the heterogeneously doped region.

"In example embodiments, the homogeneously doped region may include a first homogeneously doped region adjacent to the source region of the second transistor and a second homogeneously doped region adjacent to the drain region of the second transistor, and the channel forming region of the second transistor may further include a heterogeneously doped region connecting the first homogeneously doped region with the second homogeneously doped region.

"In example embodiments, doping concentrations of the first and second homogeneously doped regions may be lower than those of the source and drain regions of the second transistor.

"In example embodiments, a doping concentration of the first homogeneously doped region decreases from the source region of the second transistor to the heterogeneously doped region, and a doping concentration of the second homogeneously doped region decreases from the drain region of the second transistor to the heterogeneously doped region.

"In example embodiments, the device may further include a fourth transistor including source and drain regions, whose conductivity type may be the same as those of the source and drain regions of the first transistor, and a channel forming region between the source and drain regions. The channel forming region of the fourth transistor may be in a substantially undoped state.

"In example embodiments, a threshold voltage of the fourth transistor may be lower than that of the first transistor and higher than that of the second transistor.

"In example embodiments, the device may further include device isolation layers on the substrate. The nano-sized active region extends from the substrate to between the device isolation layers, thereby having a fin-shaped structure.

"In example embodiments, the fin-shaped nano-sized active region has a width of about 10 nm or less.

"In example embodiments, each of the first and second transistors may further include a gate dielectric and a gate electrode that may be sequentially stacked on the nano-sized active region, and the gate electrode may include a portion extending below the nano-sized active region.

"In example embodiments, the semiconductor device may include a first region provided with the first and second transistors and a second region provided with a fifth transistor, and the fifth transistor may include source and drain regions having a different conductivity type from the source and drain regions of the first transistor and a channel forming region provided between the source and drain regions, and the channel forming region of the fifth transistor may include a homogeneously doped region having the same conductivity type as those of the source and drain regions of the fifth transistor.

"In example embodiments, each of the first and fifth transistors may include a gate electrode, and the gate electrodes of the first and fifth transistors include the same metal material as each other.

"In example embodiments, the gate electrode of the first transistor has the same work-function as that of the fifth transistor.

"According to example embodiments of the inventive concepts, a semiconductor device, including a first transistor, a second transistor, and a third transistor, each of which may include a fin portion protruding from a substrate, source and drain regions in respective end portions of the fin portion, and a channel forming region between the source and drain regions. The source and drain regions of each of the first, second, and third transistors have the same conductivity type, the channel forming region of the second transistor may include a homogeneously doped region, whose conductivity type may be different from that of the channel forming region of the first transistor and may be the same as those of the source and drain regions of the second transistor, and the channel forming region of the third transistor may include a first homogeneously doped region connected to the source region of the third transistor and having the same conductivity type as the source region of the second transistor, a second homogeneously doped region connected to the drain region of the third transistor and having the same conductivity type as the source region of the second transistor, and a heterogeneously doped region connecting the first homogeneously doped region to the second homogeneously doped region and having a different conductivity type from the source and drain regions of the second transistor.

"In example embodiments, a threshold voltage of the third transistor may be lower than that of the first transistor and higher than that of the second transistor.

"In example embodiments, the homogeneously doped region of the second transistor may be configured to have an inversion region, when the second transistor may be applied with a voltage lower than a threshold voltage thereof, and each of the first and second homogeneously doped regions of the third transistor may be configured to have an inversion region, when the third transistor may be applied with a voltage lower than a threshold voltage thereof.

"In example embodiments, a depth of the inversion region of the second transistor from a surface of the fin portion may be substantially the same as those of the source and drain regions of the second transistor, and a depth of the inversion region of the third transistor from the surface of the fin portion may be substantially the same as those of the source and drain regions of the third transistor.

"In example embodiments, the fin portion has a width of about 10 nm or less.

"In example embodiments, the device may further include a fourth transistor including source and drain regions having the same conductivity type as the source and drain regions of the first transistor and a channel forming region between the source and drain regions. The channel forming region of the fourth transistor may be in a substantially undoped state.

"In example embodiments, a threshold voltage of the fourth transistor may be lower than that of the first transistor and higher than that of the second transistor.

"In example embodiments, a doping concentration of the homogeneously doped region of the second transistor may be lower than those of the source and drain regions of the second transistor.

"In example embodiments, the semiconductor device may include a first region provided with the first and second transistors and a second region provided with a fifth transistor, and the fifth transistor may include source and drain regions having a different conductivity type from the source and drain regions of the first transistor and a channel forming region provided between the source and drain regions, and the channel forming region of the fifth transistor may include a homogeneously doped region having the same conductivity type as the source and drain regions of the fifth transistor.

"In example embodiments, each of the first and fifth transistors may include a gate electrode, and the gate electrodes of the first and fifth transistors include the same metal material as each other.

"In example embodiments, the gate electrode of the first transistor has the same work-function as that of the fifth transistor.

"According to example embodiments of the inventive concepts, an SRAM device may include a driver transistor including a source region that may be connected to a ground line, a transfer transistor including a drain region that may be connected to a bit line, the transfer transistor being connected in series to the driver transistor, and a load transistor including source and drain regions that may be electrically connected to a power line and a drain region of the driver transistor, respectively. The load transistor may be a MOS transistor having a different conductivity type from the driver and transfer transistors, gate electrodes of the load, driver, or transfer transistors may include the same metal material, and at least one of the load, driver, and transfer transistors may be configured in such a way that a channel forming region thereof may include a homogeneously doped region having the same conductivity type as the source and drain regions thereof.

"In yet other example embodiments, a semiconductor device comprises a junctionless nanotransistor and a junction nanotransistor integrated on a common substrate

"In some embodiments, the junction nanotransistor comprises spaced apart source and drain regions in a nano-sized active region on the common substrate and a gate on the nano-sized active region therebetween, at least a portion of the nano-sized active region adjacent the gate being a different conductivity type than the spaced apart source and drain regions.

"In other embodiments, the junction nanotransistor comprises spaced apart source and drain regions in a nano-sized active region on the common substrate and a gate on the nano-sized active region therebetween, at least a portion of the nano-sized active region adjacent the gate being undoped.

"In other embodiments, the junction nanotransistor comprises spaced apart source and drain regions in a nano-sized active region on the common substrate and a gate on the nano-sized active region therebetween, the nano-sized active region adjacent the gate comprising a first region that is a different conductivity type than the spaced apart source and drain regions and a second region that is a same conductivity type as the spaced apart source and drain regions.

"In other embodiments, the junctionless nanotransistor comprises first and second junctionless nanotransistors that are of opposite conductivity types.

"In other embodiments, the junctionless nanotransistor comprises spaced apart source and drain regions in a nano-sized active region on the common substrate and a gate on the nano-sized active region therebetween, the spaced apart source and drain regions and the nano-sized active region adjacent the gate being a same conductivity type.

"In other embodiments, the junctionless nanotransistor and the junction nanotransistor both comprise spaced apart source and drain regions in a nano-sized active region on the common substrate and a gate on the nano-sized active region therebetween, the spaced apart source and drain regions of the junctionless nanotransistor and of the junction nanotransistor all being of same conductivity type.

BRIEF DESCRIPTION OF THE DRAWINGS

"Example embodiments will be more clearly understood from the following brief description taken in conjunction with the accompanying drawings. The accompanying drawings represent non-limiting, example embodiments as described herein.

"FIG. 1 is a plan view illustrating a semiconductor device according to example embodiments of the inventive concepts.

"FIG. 2 is a diagram illustrating vertical sections of the first transistor taken along lines A-A' and I-I' of FIG. 1.

"FIG. 3 is a diagram illustrating vertical sections of the first transistor taken along lines B-B' and II-II' of FIG. 1.

"FIG. 4 is a diagram illustrating vertical sections of the first transistor taken along lines C-C' and III-III' of FIG. 1.

"FIG. 5 is a diagram illustrating vertical sections of the first transistor taken along lines D-D' and IV-IV' of FIG. 1.

"FIG. 6 is a diagram illustrating vertical sections of the first transistor taken along lines E-E' and V-V' of FIG. 1.

"FIG. 7 is a schematic diagram illustrating an inversion region according to example embodiments of the inventive concepts.

"FIG. 8 is a schematic diagram illustrating on- and off-states of the first transistor.

"FIG. 9 is a schematic diagram illustrating on- and off-states of the second transistor.

"FIG. 10 is a schematic diagram illustrating on- and off-states of the third transistor,

"FIG. 11 is a schematic diagram illustrating on- and off-states of the fourth transistor.

"FIGS. 12A through 17A are sectional views of the first to third transistors to describe a method of fabricating a semiconductor device according to example embodiments of the inventive concepts.

"FIGS. 12B through 17B are sectional views of the fourth and fifth transistors to describe a method of fabricating a semiconductor device according to example embodiments of the inventive concepts.

"FIGS. 18A through 18C are sectional views illustrating a method of fabricating a semiconductor device according to other example embodiments of the inventive concepts.

"FIG. 19 is a schematic diagram illustrating a nano-sized active region of a semiconductor device according to other example embodiments of the inventive concepts.

"FIG. 20 is a schematic diagram illustrating a nano-sized active region of a semiconductor device according to still other example embodiments of the inventive concepts.

"FIG. 21 is an equivalent circuit diagram of a CMOS SRAM cell including a fin field effect transistor according to example embodiments of the inventive concepts.

"FIG. 22 is a block diagram of an electronic system including a semiconductor device according to example embodiments of the inventive concepts.

"It should be noted that these figures are intended to illustrate the general characteristics of methods, structure and/or materials utilized in certain example embodiments and to supplement the written description provided below. These drawings are not, however, to scale and may not precisely reflect the precise structural or performance characteristics of any given embodiment, and should not be interpreted as defining or limiting the range of values or properties encompassed by example embodiments. For example, the relative thicknesses and positioning of molecules, layers, regions and/or structural elements may be reduced or exaggerated for clarity. The use of similar or identical reference numbers in the various drawings is intended to indicate the presence of a similar or identical element or feature."

For additional information on this patent application, see: Suk, Sung-Dae; Oh, Changwoo; Park, Sungil. Integrated Junction and Junctionless Nanotransistors. Filed November 25, 2013 and posted June 5, 2014. Patent URL: http://appft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&u=%2Fnetahtml%2FPTO%2Fsearch-adv.html&r=4880&p=98&f=G&l=50&d=PG01&S1=20140529.PD.&OS=PD/20140529&RS=PD/20140529

Keywords for this news article include: Patents, Electronics, Semiconductor.

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Source: Electronics Newsweekly


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