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Researchers Submit Patent Application, "High Voltage Semiconductor Devices", for Approval

June 18, 2014



By a News Reporter-Staff News Editor at Electronics Newsweekly -- From Washington, D.C., VerticalNews journalists report that a patent application by the inventors Shrivastava, Mayank (Essex Junction, VT); Shojaei Baghini, Maryam (Mumbai, IN); Russ, Cornelius Christian (Diedorf, DE); Gossner, Harald (Riemerling, DE); Rao, Ramgopal (Mumbai, IN), filed on January 30, 2014, was made available online on June 5, 2014.

No assignee for this patent application has been made.

News editors obtained the following quote from the background information supplied by the inventors: "Semiconductor devices are used in a large number of electronic devices, such as computers, cell phones, and others. Semiconductor devices comprise integrated circuits that are formed on semiconductor wafers by depositing many types of thin films of material over the semiconductor wafers, and patterning the thin films of material to form the integrated circuits. Integrated circuits include field-effect transistors (FETs) such as metal oxide semiconductor (MOS) transistors.

"One of the goals of the semiconductor industry is to continue shrinking the size and increasing the speed of individual FETs. To achieve these goals, planar fully depleted SOI devices, and non-planar devices such as fin FETs (FINFETs) or multiple gate transistors will be used in sub 32 nm transistor nodes. For example, FINFETs not only improve areal density but also improve gate control of the channel, which is a serious threat to scaling planar transistors.

"However, besides high performance devices, which are typically low voltage circuits, other high voltage devices are essential for every technology. Example of high voltage devices include input/output devices. High voltage devices are traditionally produced using a thicker gate oxide, longer channel length, changing the doping etc. However, such options are not feasible in non-planar device technologies which require fixed design space to minimize process variations and reduce process complexities.

"Accordingly, what is needed in the art are high voltage devices that are compatible with non traditional device architectures and design space while at the same time overcoming the deficiencies of the prior art."

As a supplement to the background information on this patent application, VerticalNews correspondents also obtained the inventors' summary information for this patent application: "In accordance with an embodiment of the present invention, a semiconductor device comprises a first source of a first doping type disposed in a substrate. A first drain of the first doping type is disposed in the substrate. A first fin is disposed between the first source and the first drain. A first gate is disposed over the first fin. A second fin intersects a region of the first fin between the first gate and the first drain.

"In accordance with an alternative embodiment of the present invention, a semiconductor device comprises a first source of a first doping type disposed in a substrate. A first drain of the first doping type is disposed in the substrate. A first gate is disposed between the first source and the first drain. A first channel is disposed under the first gate. A first extension region of the first doping type is proximate the first drain. A first doped region of a second doping type is disposed in the substrate. The second doping type is opposite to the first doping type. The first extension region contacts the first doped region. The first doped region is electrically separated from the first channel by the first extension region.

"In accordance with yet another embodiment of the present invention, a semiconductor device comprises a first source of a first doping type disposed in a substrate. A first drain of the first doping type is disposed in the substrate. A first gate region is disposed between the first source and the first drain. A first channel region is disposed under the first gate region. A first extension region of the first doping type is disposed between the first gate and the first drain. The first extension region is part of a first fin disposed in or over the substrate. A first isolation region is disposed between the first extension region and the first drain. A first well region of the first doping type is disposed under the first isolation region. The first well region electrically couples the first extension region with the first drain.

"The foregoing has outlined rather broadly the features of an embodiment of the present invention in order that the detailed description of the invention that follows may be better understood. Additional features and advantages of embodiments of the invention will be described hereinafter, which form the subject of the claims of the invention. It should be appreciated by those skilled in the art that the conception and specific embodiments disclosed may be readily utilized as a basis for modifying or designing other structures or processes for carrying out the same purposes of the present invention. It should also be realized by those skilled in the art that such equivalent constructions do not depart from the spirit and scope of the invention as set forth in the appended claims.

BRIEF DESCRIPTION OF THE DRAWINGS

"For a more complete understanding of the present invention, and the advantages thereof, reference is now made to the following descriptions taken in conjunction with the accompanying drawing, in which:

"FIG. 1, which includes FIGS. 1a-1f, illustrates of a FINFET SOI device in accordance with an embodiment of the invention, wherein FIG. 1a illustrates a top view and wherein FIGS. 1b-1f illustrate cross sectional views;

"FIG. 2 illustrates an alternative embodiment of a FINFET SOI device having a plurality of gate lines;

"FIG. 3, which includes FIGS. 3a-3d, illustrates a planar SOI device in accordance with an embodiment of the invention, wherein FIG. 3a illustrates a top view and FIG. 3b-3c illustrate cross sectional views;

"FIG. 4 illustrates a top view of a planar SOI device having a split gate in accordance with an embodiment of the invention;

"FIG. 5 illustrates a top view of an alternative embodiment of a FINFET SOI device;

"FIG. 6, which includes FIGS. 6a-6d, illustrates a bulk FINFET device in accordance with an embodiment of the invention, wherein FIG. 6a illustrates a top view and FIGS. 6b-6d illustrate cross sectional views;

"FIG. 7, which includes FIGS. 7a-7e, illustrates cross sectional views of a bulk FINFET device in accordance with embodiments of the invention;

"FIG. 8, which includes FIGS. 8a-8c, illustrates a bulk FINFET device in accordance with an alternative embodiment of the invention, wherein FIG. 8a illustrates a top view and FIGS. 8b and 8c illustrate alternative cross sectional views;

"FIG. 9, which includes 9a-9c, illustrates a bulk FINFET having a plurality of gate lines in accordance with an embodiment of the invention, wherein FIG. 9a illustrates a top view and FIGS. 9b and 9c illustrate alternative cross sectional views;

"FIG. 10, which includes FIGS. 10a-10c, illustrates a bulk FINFET device in accordance with an alternative embodiment;

"FIG. 11 illustrates a bulk FINFET device in accordance with an alternative embodiment;

"FIG. 12 illustrates a SOI FINFET device in accordance with an alternative embodiment;

"FIG. 13 illustrates a planar SOI device in accordance with an alternative embodiment; and

"FIG. 14 illustrates a bulk FINFET device in accordance with an alternative embodiment.

"Corresponding numerals and symbols in the different figures generally refer to corresponding parts unless otherwise indicated. The figures are drawn to clearly illustrate the relevant aspects of the embodiments and are not necessarily drawn to scale."

For additional information on this patent application, see: Shrivastava, Mayank; Shojaei Baghini, Maryam; Russ, Cornelius Christian; Gossner, Harald; Rao, Ramgopal. High Voltage Semiconductor Devices. Filed January 30, 2014 and posted June 5, 2014. Patent URL: http://appft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&u=%2Fnetahtml%2FPTO%2Fsearch-adv.html&r=4888&p=98&f=G&l=50&d=PG01&S1=20140529.PD.&OS=PD/20140529&RS=PD/20140529

Keywords for this news article include: Patents, Electronics, High Voltage, Semiconductor.

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Source: Electronics Newsweekly


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