News Column

Patent Issued for Variable Resistance Memory Devices

June 18, 2014



By a News Reporter-Staff News Editor at Electronics Newsweekly -- According to news reporting originating from Alexandria, Virginia, by VerticalNews journalists, a patent by the inventor Lee, Jaekyu (Yongin-si, KR), filed on September 23, 2011, was published online on June 3, 2014.

The assignee for this patent, patent number 8742388, is Samsung Electronics Co., Ltd. (Gyeonggi-Do, KR).

Reporters obtained the following quote from the background information supplied by the inventors: "Example embodiments of the inventive concepts relate generally to memory semiconductor devices. More particularly, example embodiments of the inventive concepts relate to variable resistance memory devices (VRMD) and methods of fabricating the same.

"Semiconductor memory devices are generally classified into volatile memory devices and nonvolatile memory devices. Volatile memory devices may lose their stored data when their power supply is interrupted. Volatiles memory devices may, for example, include a dynamic random access memory (DRAM) and a static random access memory (SRAM). Nonvolatile memory devices may maintain their stored data even when their power supply is interrupted. Nonvolatile memory devices may, for example, include a programmable read only memory (PROM), an erasable PROM (EPROM), an electrically EPROM (EEPROM) and a flash memory device.

"Semiconductor memory devices may, for example, include a ferroelectric random access memory (FRAM), a magnetic random access memory (MRAM) and a phase change random access memory (PRAM). Material constituting these semiconductor memory devices may have a different resistance depending on a current forced thereto or a voltage applied thereto, and may have a characteristic maintaining a resistance even when a current supply or a voltage supply is interrupted."

In addition to obtaining background information on this patent, VerticalNews editors also obtained the inventor's summary information for this patent: "Example embodiments of the inventive concepts may provide variable resistance memory devices with an improved electric property and/or enhanced reliability. Other example embodiments of the inventive concepts may provide methods of fabricating variable resistance memory devices with an improved electric property and/or enhanced reliability.

"According to an example embodiment of the inventive concepts, a variable resistance memory device may include a semiconductor layer including a first doped region, at least one second doped region, and at least one third doped region, a variable resistance pattern on the semiconductor layer, at least one lower electrode between the semiconductor layer and the variable resistance pattern, and a first metal silicide pattern in contact with the semiconductor layer. The third doped region may be spaced apart from the first metal silicide pattern, the first doped region may be spaced apart from the third doped region, and a second doped region may be interposed between the first and third doped regions and be in contact with the first metal silicide pattern. The first doped region may have the same conductivity type as the third doped region and a different conductivity type from the second doped region.

"According to some example embodiments, the first metal silicide pattern may be spaced apart from the lower electrode and the first doped region, and the lower electrode may be spaced apart from the second doped region. According to other example embodiments, the second doped region may include a lightly doped region in contact with the third doped region and a heavily doped region spaced apart from the third doped region. According to still other example embodiments, the first metal silicide pattern may be in contact with the heavily doped region and spaced apart from the lightly doped region. According to even other example embodiments, the lightly doped region may be provided on the first doped region, the heavily doped region may be provided on the lightly doped region, and the first metal silicide pattern may be provided on the heavily doped region.

"According to yet other example embodiments, the device may further include a contact hole penetrating the first metal silicide pattern and the heavily doped region to expose the lightly doped region. The third doped region may be provided in the lightly doped region under the contact hole. According to further example embodiments, the device may further include a contact hole penetrating the first metal silicide pattern and the heavily doped region to expose the lightly doped region, and the third doped region may be provided in the contact hole. According to still further example embodiments, the device may further include an insulating spacer disposed on a sidewall of the contact hole. According to even further example embodiments, the device may further include a second metal silicide pattern interposed between the lower electrodes and the third doped region and being in contact with the third doped region.

"According to yet further example embodiments, the device may further include conductive lines disposed on the variable resistance pattern, and the conductive line may extend to cross the first metal silicide pattern and the first metal silicide pattern extends to cross the conductive line. According to yet further example embodiments, the at least one lower electrode may include a plurality of lower electrodes arranged two-dimensionally on the semiconductor layer, and the at least one third doped region includes a plurality of third doped regions, each of which may be disposed below the respective lower electrodes and separated from each other. According to yet further example embodiments, the at least one second doped region may include a plurality of second doped regions separated from each other by a device isolation layer and configured to extend parallel to the first metal silicide pattern.

"According to other example embodiments of the inventive concepts, a method of fabricating a variable resistance memory device may include forming second doped regions in a substrate, forming a metal silicide pattern in contact with the second doped region, forming a contact hole penetrating the metal silicide pattern to expose the second doped region, forming an insulating spacer on a sidewall of the contact hole, forming a lower electrode in the contact hole, forming a phase changeable material pattern on the lower electrode, and forming a third doped region having a different conductivity type from the second doped region between the second doped regions and the lower electrode.

"According to some example embodiments, the third doped region and the substrate have a first conductivity type, and the second doped region has a second conductivity type different from the first conductivity type. According to other example embodiments, the forming of the second doped regions may include forming a lightly doped region to a first depth from a top surface of the substrate and forming a heavily doped region to a second depth less than the first depth from the top surface of the substrate. According to still other example embodiments, the forming of the contact hole may include performing a first etch step using the metal silicide pattern as an etch stop layer and performing a second etch step to expose the lightly doped region.

"According to even other example embodiments, the method may further include forming a device isolation layer between the second doped regions. The forming of the metal silicide pattern may include recessing an upper portion of the device isolation layer to a depth less than the first depth. According to yet other example embodiments, the forming of the third doped region may include doping a portion of the second doped region exposed by the contact hole with impurities of the first conductivity type. According to further example embodiments, the third doped region may be formed on the second doped region exposed by the contact hole. According to still further example embodiments, the forming of the third doped region may include forming a semiconductor epitaxial layer on the second doped region using a selective epitaxial growth technique, and a lower portion of the semiconductor epitaxial layer may be formed to have the same conductivity type as the second doped region.

"According to at least one embodiment, a variable resistance memory device, includes a semiconductor layer, a variable resistance element on the semiconductor layer, a bipolar junction transistor (BJT) at least partially in the semiconductor layer, an emitter of the BJT connected to an electrode of the variable resistance element, and a silicide layer on the semiconductor layer, a base of the BJT being connected to the silicide layer, the base and the emitter separating the variable resistance element from the silicide layer.

"According to at least one example embodiment, a variable resistance memory device includes a semiconductor layer with a first doped region of a first conductivity type, at least one second doped region of a second conductivity type, and at least one third doped region of the first conductivity type, the first doped region being spaced apart from the third doped region, the second doped region being between the first and third doped regions, a variable resistance pattern on the semiconductor layer, at least one lower electrode between the semiconductor layer and the variable resistance pattern, and a first metal silicide pattern in contact with the semiconductor layer, the first metal silicide pattern being spaced apart from the third doped region, the second doped region being in contact with the first metal silicide pattern.

"According to at least one example embodiment, a method of fabricating a variable resistance memory device includes forming a first doped region of a first conductivity type in a substrate, forming a metal silicide pattern in contact with the first doped region, forming a contact hole penetrating the metal silicide pattern to expose the first doped region, forming an insulating spacer on a sidewall of the contact hole, forming a lower electrode in the contact hole, forming a phase change material pattern on the lower electrode, and forming a second doped region of a second conductivity type between the first doped region and the lower electrode."

For more information, see this patent: Lee, Jaekyu. Variable Resistance Memory Devices. U.S. Patent Number 8742388, filed September 23, 2011, and published online on June 3, 2014. Patent URL: http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=8742388.PN.&OS=PN/8742388RS=PN/8742388

Keywords for this news article include: Semiconductor, Random Access Memory, Samsung Electronics Co. Ltd..

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Source: Electronics Newsweekly


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