News Column

Patent Issued for Stacked Multilayer Structure and Manufacturing Method

June 18, 2014



By a News Reporter-Staff News Editor at Electronics Newsweekly -- From Alexandria, Virginia, VerticalNews journalists report that a patent by the inventors Mizukami, Makoto (Kawasaki, JP); Kamigaichi, Takeshi (Yokohama, JP), filed on October 18, 2013, was published online on June 3, 2014.

The patent's assignee for patent number 8742586 is Kabushiki Kaisha Toshiba (Minato-ku, JP).

News editors obtained the following quote from the background information supplied by the inventors: "The present invention is related to a stacked multilayer structure, a manufacturing method thereof, and a semiconductor device using said stacked multilayer structure.

"The demand for miniature and large capacity nonvolatile semiconductor devices is increasing. In order to realize this miniaturization and large scale capacity, a number of devices in which semiconductor elements such as memory cell transistors are arranged three dimensionally have been proposed. For example, such devices are disclosed in the United States Patent Publication No. US-20020154556-A1, the U.S. Pat. No. 5,599,724, U.S. Pat. No. 5,707,885, and Masuoka et al, 'Novel Ultrahigh-Density Flash Memory With a Stacked-Surrounding Gate Transistor (S-SGT) Structured Cell' IEEE TRANSACTIONS ON ELECTRON DEVICES, Vol. 50, N04, pp 945-951, April 2003.

"In such devices in which semiconductor elements and the like are arranged three dimensionally, a plurality of conducting layers are stacked to form a stacked multilayer structure, each of said plurality of conducting layers being connected to several electrodes of said elements positioned on the same layer. And there is a need to connect each of said plurality of conducting layers to a driving circuit. Thereupon, there is a need to form efficiently these connection structures while keeping their reliability."

As a supplement to the background information on this patent, VerticalNews correspondents also obtained the inventors' summary information for this patent: "A stacked multilayer structure according to an embodiment of the present invention comprises: a stacked layer part including a plurality of conducting layers and a plurality of insulating layers, said plurality of insulating layers being stacked alternately with each layer of said plurality of conducting layers, one of said plurality of insulating layers being a topmost layer among said plurality of conducting layers and said plurality of insulating layers; and a plurality of contacts, each contact of said plurality of contacts being formed from said topmost layer and each contact of said plurality of contacts being in contact with a respective conducting layer of said plurality of conducting layers, a side surface of each of said plurality of contacts being insulated from said plurality of conducting layers via an insulating film.

"A nonvolatile semiconductor device according to an embodiment of the present invention comprises: a stacked layer part including a plurality of conducting layers, a plurality of insulating layers and a plurality of semiconductor pillars, said plurality of insulating layers being stacked alternately with each layer of said plurality of conducting layers, one of said plurality of insulating layers being a topmost layer among said plurality of conducting layers and said plurality of insulating layers, and each of said plurality of semiconductor pillars having a nonvolatile memory cell around the section of penetration into each of said plurality of conducting layers; a plurality of contacts, each contact of said plurality of contacts being formed from said topmost layer and each contact of said plurality of contacts being in contact with a respective conducting layer of said plurality of conducting layers, a side surface of each of said plurality of contacts being insulated from said plurality of conducting layers via an insulating film; and a driving circuit being connected to each of said plurality of conducting layers respectively via said plurality of contacts.

"A manufacturing method according to an embodiment of the present invention of a stacked multilayer structure comprises: stacking a conducting layer and a plurality of insulating layer alternately, one of said insulating layer being a topmost layer among a plurality of insulating layers and a plurality of conducting layers; forming a plurality of contact holes, each of said plurality of contact holes being in contact with a top surface of said conducting layers respectively from said topmost layer; forming an insulating film on a side surface of said plurality of contact holes; and forming contacts by depositing conducting material inside said plurality of contact holes."

For additional information on this patent, see: Mizukami, Makoto; Kamigaichi, Takeshi. Stacked Multilayer Structure and Manufacturing Method. U.S. Patent Number 8742586, filed October 18, 2013, and published online on June 3, 2014. Patent URL: http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=8742586.PN.&OS=PN/8742586RS=PN/8742586

Keywords for this news article include: Electronics, Semiconductor, Kabushiki Kaisha Toshiba.

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Source: Electronics Newsweekly


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