News Column

Patent Issued for Semiconductor Wafer and Its Manufacture Method, and Semiconductor Chip

June 18, 2014



By a News Reporter-Staff News Editor at Electronics Newsweekly -- From Alexandria, Virginia, VerticalNews journalists report that a patent by the inventors Yoshizawa, Kazutaka (Yokohama, JP); Ema, Taiji (Yokohama, JP), filed on February 15, 2011, was published online on June 3, 2014.

The patent's assignee for patent number 8742547 is Fujitsu Semiconductor Limited (Yokohama, JP).

News editors obtained the following quote from the background information supplied by the inventors: "A number of semiconductor chips are formed on a semiconductor wafer involving scribe areas. The semiconductor wafer is cut along the scribe areas and separated into individual semiconductor chips. If cracks formed in the scribe areas during scribing propagate into the semiconductor chip, the chips are broken.

"A moisture proof ring is generally formed along the border of a semiconductor chip. The technique of further forming a metal ring outside the moisture proof ring to suppress propagation of cracks into the semiconductor chip has been proposed (Japanese Patent Laid-open Publication No. 2008-270720). Techniques of enhancing the crack propagation suppressing effects of the metal ring have long been desired."

As a supplement to the background information on this patent, VerticalNews correspondents also obtained the inventors' summary information for this patent: "According to one aspect of the present invention, a semiconductor wafer includes:

"a first semiconductor chip area formed with semiconductor elements;

"a second semiconductor chip area formed with semiconductor elements; and

"a scribe area sandwiched between the first semiconductor chip area and the second semiconductor chip area;

"wherein:

"The first semiconductor chip area includes a first metal ring surrounding semiconductor elements formed in the first semiconductor chip area;

"The first metal ring is constituted of a plurality of metal layers including an lower metal layer and an upper metal layer superposed upon the lower metal layer, and the upper metal layer is superposed upon the lower metal layer in such a manner that an outer side wall of an upper metal layer in the first semiconductor chip area is flush with the outer side wall of a lower metal layer or is at an inner position of the first semiconductor chip area relative to the outer side wall of the lower metal layer.

"The object and advantages of the invention will be realized and attained by means of the elements and combinations particularly pointed out in the claims.

"It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are not restrictive of the invention, as claimed."

For additional information on this patent, see: Yoshizawa, Kazutaka; Ema, Taiji. Semiconductor Wafer and Its Manufacture Method, and Semiconductor Chip. U.S. Patent Number 8742547, filed February 15, 2011, and published online on June 3, 2014. Patent URL: http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=8742547.PN.&OS=PN/8742547RS=PN/8742547

Keywords for this news article include: Electronics, Fujitsu Semiconductor Limited.

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Source: Electronics Newsweekly