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Patent Issued for Semiconductor Devices Including Design for Test Capabilities and Semiconductor Modules and Test Systems Including Such Devices

June 18, 2014



By a News Reporter-Staff News Editor at Electronics Newsweekly -- From Alexandria, Virginia, VerticalNews journalists report that a patent by the inventors Kim, Seok-Il (Seoul, KR); Lee, Ho-Suk (Hwaseong-si, KR); Han, You-Keun (Yongin-si, KR); Kim, Yang-Ki (Seoul, KR), filed on October 29, 2010, was published online on June 3, 2014.

The patent's assignee for patent number 8742780 is Samsung Electronics Co., Ltd. (KR).

News editors obtained the following quote from the background information supplied by the inventors: "Example embodiments relate to semiconductor devices, and more particularly to semiconductor devices adopting design-for-test (DFT) schemes, and semiconductor modules and test systems including such semiconductor devices.

"Semiconductor devices generally include input/output (I/O) terminals to transmit and receive signals through transmission lines that are coupled to an external device. An impedance of the I/O terminal should be sufficiently matched to an impedance of the transmission line in order to reduce and/or prevent signal reflections at the interface between the semiconductor device and the transmission line. However, as the operating speed of semiconductor devices has increased, it has become more difficult to match the impedance of an I/O terminal to the impedance of an associated transmission line, and the signals transmitted over the transmission lines may be distorted due to such impedance mismatching.

"Various impedance matching methods have been developed to match the impedance of an I/O terminal to the impedance of an associated transmission line. For example, some semiconductor memory devices such as the Double Data Rate 3 (DDR3) Synchronous Dynamic Random Access Memory (SDRAM) devices perform the impedance matching by using a ZQ calibration unit and a ZQ terminal included in the semiconductor memory device and an external ZQ resistor connected between the ZQ terminal and a ground voltage."

As a supplement to the background information on this patent, VerticalNews correspondents also obtained the inventors' summary information for this patent: "Some example embodiments provide a semiconductor device that is configured to test an external electrical connection between a resistor terminal and an external resistor.

"Some example embodiments provide a semiconductor module and/or a test system including the semiconductor device.

"According to some example embodiments, a semiconductor device includes a resistor terminal, a reference voltage generator and a detector. The resistor terminal is connected to an external resistor. The reference voltage generator generates at least one reference voltage. The detector generates a detection signal based at least in part on a voltage of the resistor terminal (the 'resistor terminal voltage') and the at least one reference voltage. The detection signal may indicate a state of an electrical connection to the resistor terminal.

"The electrical connection may be an external electrical connection between the resistor terminal and the external resistor. The detection signal may indicate whether the state of the external electrical connection between the resistor terminal and the external resistor is normal or abnormal. and The at least one reference voltage may be based on a power supply voltage.

"The semiconductor device may further include at least one input/output (I/O) terminal connected to the detector. The semiconductor device may output the detection signal through the at least one I/O terminal. The at least one I/O terminal may be a data I/O terminal in some embodiments.

"In some embodiments, the at least one reference voltage may include a first reference voltage. The detector may include a comparator. The comparator may compare the resistor terminal voltage and the first reference voltage to generate the detection signal.

"The detection signal may have a first logic level when the external electrical connection is normal, and the detection signal may have a second logic level when the external electrical connection is abnormal.

"The first reference voltage may have a level between a normal level and an abnormal level. The normal level may be a level of the resistor terminal voltage when the external electrical connection is normal, and the abnormal level may be the level of the resistor terminal voltage when the external electrical connection is abnormal.

"In other embodiments, the semiconductor device may further include an impedance calibration unit that is connected to the resistor terminal. The impedance calibration unit may calibrate an input impedance and/or an output impedance for the semiconductor device in response to an impedance calibration signal. The semiconductor device may be configured to simultaneously output the detection signal and calibrate the input impedance and/or output impedance for the semiconductor device.

"The detection signal may further indicate whether an internal electrical connection between the resistor terminal and the impedance calibration unit is not mai or abnormal.

"In some embodiments, the detector may include a first comparator, a second comparator and an OR gate. The first comparator may compare the resistor terminal voltage with a first reference voltage of the at least one reference voltage to generate a first comparison signal. The second comparator may compare the resistor terminal voltage with a second reference voltage of the at least one reference voltage to generate a second comparison signal. A level of the second reference voltage may be lower than a level of the first reference voltage. The OR gate may perform an OR operation on the first comparison signal and the second comparison signal to generate the detection signal.

"The first reference voltage may be a voltage that is between a level of the resistor terminal voltage when both the external electrical connection and the internal electrical connection are normal and a level of the resistor terminal voltage when the external electrical connection is abnormal. The second reference voltage may be a voltage that is between the level of the resistor terminal voltage when both the external electrical connection and the internal electrical connection are normal and the level of the resistor terminal voltage when the internal electrical connection is abnormal.

"The detection signal may have a first logic level when both of the external electrical connection and the internal electrical connection are normal, and the detection signal may have a second logic level when at least one of the external electrical connection and the internal electrical connection is abnormal.

"The first reference voltage may have the level between a normal level and a first abnormal level, and the second reference voltage may have the level between the normal level and a second abnormal level. The normal level may be a level of the resistor terminal voltage when both of the external electrical connection and the internal electrical connection are normal, the first abnormal level may be the level of the resistor terminal voltage when the external electrical connection is abnormal, and the second abnormal level may be the level of the resistor terminal voltage when the internal electrical connection is abnormal.

"The semiconductor device may output the detection signal in response to the impedance calibration signal.

"The semiconductor device may further include a test mode controller. The test mode controller may generate a test mode register set (MRS) signal based on a command signal and an address signal. The reference voltage generator may generate the at least one reference voltage and the detector generates the detection signal when the test MRS signal is enabled.

"According to other example embodiments, a test system includes a semiconductor module. The semiconductor module includes a module board, a plurality of resistors on the module board and a plurality of semiconductor devices on the module board. Each of the plurality of semiconductor devices includes a resistor terminal, a reference voltage generator and a detector. The resistor terminal is connected to a respective one of the plurality of resistors. The reference voltage generator generates at least one reference voltage. The detector generates a detection signal based at least in part on a resistor terminal voltage and the at least one reference voltage. The detection signal indicates a state of an electrical connection to the resistor terminal.

"The electrical connection may be an external electrical connection between the resistor terminal and the respective one of the plurality of resistors. The detection signal may indicate whether the state of the external electrical connection between the resistor terminal and the respective one of the plurality of resistors is normal or abnormal. Each of the plurality of semiconductor devices may further include an impedance calibration unit connected to the resistor terminal. The impedance calibration unit may calibrate an input impedance and/or an output impedance for a respective one of the plurality of semiconductor devices. The detection signal may further indicate whether an internal electrical connection between the resistor terminal and the impedance calibration unit is normal or abnormal.

"The test system may further include a test device. The test device may test the semiconductor module to determine whether electrical connections between the plurality of semiconductor devices and the plurality of resistors are normal or abnormal.

"The test device may include a test controller that generates a command signal and an address signal controlling the semiconductor module.

"Each of the plurality of semiconductor devices may further include a test mode controller. The test mode controller may generate a test mode register set (MRS) signal based on the command signal and the address signal. The reference voltage generator may generate the at least one reference voltage, and the detector may generate the detection signal when the test MRS signal is enabled.

"Each of the plurality of semiconductor devices may further include at least one input/output (I/O) terminal connected to the detector. Each of the plurality of semiconductor devices may output the detection signal through the at least one I/O terminal.

"According to other example embodiments, a semiconductor device includes a semiconductor integrated circuit and an external resistor. The semiconductor integrated circuit includes a resistor terminal, an impedance calibration unit, a reference voltage generator and a detector. The impedance calibration unit is connected to the resistor terminal and is configured to calibrate an input impedance and/or an output impedance for the semiconductor device in response to an impedance calibration signal. The reference voltage generator is configured to generate at least one reference voltage. The detector is configured to generate a detection signal based at least in part on a voltage of the resistor terminal and the at least one reference voltage, the detection signal indicates a state of at least one of an external electrical connection between the resistor terminal and the external resistor and an internal electrical connection between the resistor terminal and the impedance calibration unit. The external resistor is connected to the resistor terminal.

"The detection signal may indicate whether the state of at least one of the external electrical connection and the internal electrical connection is normal or abnormal.

"The semiconductor device may further include at least one input/output (I/O) terminal connected to the detector. the semiconductor device may be configured to substantially simultaneously output the detection signal through the at least one I/O terminal and perform an impedance calibrating operation.

"The at least one reference voltage may include a first reference voltage and a second reference voltage that is lower than the first reference voltage, the detector may include a first comparator and a second comparator. The first comparator may be configured to compare the voltage of the resistor terminal and the first reference voltage to generate a first comparison signal. The second comparator may be configured to compare the voltage of the resistor terminal voltage and the second reference voltage to generate a second comparison signal.

"Accordingly, in the semiconductor device according to some example embodiments, the detector generates the detection signal, which indicates whether an electrical connection between the resistor terminal and the external resistor is normal or abnormal, and the detection signal is output through the I/O terminal. In addition, the semiconductor device simultaneously performs the impedance calibrating operation and the outputting the detection signal in response to the impedance calibration signal. Thus, the electrical connection in the semiconductor device may be effectively tested."

For additional information on this patent, see: Kim, Seok-Il; Lee, Ho-Suk; Han, You-Keun; Kim, Yang-Ki. Semiconductor Devices Including Design for Test Capabilities and Semiconductor Modules and Test Systems Including Such Devices. U.S. Patent Number 8742780, filed October 29, 2010, and published online on June 3, 2014. Patent URL: http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=8742780.PN.&OS=PN/8742780RS=PN/8742780

Keywords for this news article include: Semiconductor, Samsung Electronics Co. Ltd..

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Source: Electronics Newsweekly


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