News Column

Patent Issued for Satisfying Routing Rules during Circuit Design

June 18, 2014



By a News Reporter-Staff News Editor at Electronics Newsweekly -- A patent by the inventor Gao, Tong (Cupertino, CA), filed on October 29, 2009, was published online on June 3, 2014, according to news reporting originating from Alexandria, Virginia, by VerticalNews correspondents.

Patent number 8745565 is assigned to Synopsys, Inc. (Mountain View, CA).

The following quote was obtained by the news editors from the background information supplied by the inventors: "The present invention relates to electronic design automation (EDA). More specifically, the present invention relates to a method and a system for satisfying routing rules during routing of an integrated circuit (IC) chip design.

"Advances in semiconductor technology presently make it possible to integrate large-scale systems, including hundreds of millions of transistors, onto a single semiconductor chip. This dramatic increase in semiconductor integration densities has made it considerably more challenging to efficiently perform routing in such a large-scale IC chip.

"Routing an integrated circuit (IC) chip involves determining routes for metal wires which electrically connect integrated circuit devices to produce circuits that perform desired functions. Large scale IC chips are typically routed using routing software, which is typically referred to as a 'routing system' or 'router.'

"The routes generated by a router usually need to satisfy a set of foundry design rules. For example, a foundry may specify spacing rules that a design must meet to ensure that the design can be successfully manufactured, e.g., the foundry may specify the minimum distance between two shapes in the circuit design. A circuit design usually cannot be signed-off until all of the foundry design rules are met.

"In addition to the foundry rules, a user may also want to satisfy design rules for improving manufacturing yield. For example, moving routing shapes further apart can usually improve the manufacturing yield.

"Conventional routing techniques typically treat all rules with equal importance, and will attempt to satisfy all routing rules. Unfortunately, if the system tries to simultaneously satisfy multiple sets of rules (e.g., foundry rules and design-for-manufacturing rules, etc.), the system may never be able to sign-off a circuit design because the rules may conflict with one another (e.g., some of the foundry rules may conflict with some of the design-for-manufacturing rules)."

In addition to the background information obtained for this patent, VerticalNews journalists also obtained the inventor's summary information for this patent: "One embodiment of the present invention provides a system that attempts to satisfy routing rules during routing of an integrated circuit (IC) chip design. During operation, the system receives a routing solution for the IC chip design and a set of routing rules to be satisfied by the routing solution. The system then assigns weights to the set of routing rules, wherein a higher weight for a routing rule indicates a higher importance of the routing rule. The system additionally assigns effort levels to the set of routing rules, wherein a higher effort level for a routing rule indicates that a higher amount of resources are available to satisfy the routing rule. The system then modifies the routing solution to satisfy the routing rules based at least on the weights and the effort levels associated with the routing rules.

"In some variations, the set of routing rules include one or more hard routing rules and one or more soft routing rules. The system assigns weights to the set of routing rules by: (1) assigning a higher weight to a hard routing rule; and (2) assigning a lower weight to a soft routing rule.

"In some variations, the hard routing rules include foundry design rules, and the soft routing rules include design for manufacturing (DFM) rules and user-defined rules.

"In some variations, the effort levels can include two or more effort levels.

"In some variations, an effort level for a routing rule indicates one or more of: (1) the number of iterations that can be used to satisfy the routing rule; and (2) the number of rip-up and reroutes that can be used to satisfy the routing rule.

"In some variations, a soft routing rule which is associated with a lower weight is not required to be satisfied during the routing of the IC chip design if not satisfying the soft routing rule causes a hard routing rule to be satisfied.

"In some variations, the system determines an amount time that a router can spend on satisfying a routing rule based at least on the routing rule's effort-level and/or weight."

URL and more information on this patent, see: Gao, Tong. Satisfying Routing Rules during Circuit Design. U.S. Patent Number 8745565, filed October 29, 2009, and published online on June 3, 2014. Patent URL: http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=8745565.PN.&OS=PN/8745565RS=PN/8745565

Keywords for this news article include: Electronics, Synopsys Inc, Semiconductor.

Our reports deliver fact-based news of research and discoveries from around the world. Copyright 2014, NewsRx LLC


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Source: Electronics Newsweekly


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