The assignee for this patent, patent number 8741665, is
Reporters obtained the following quote from the background information supplied by the inventors: "The present inventive concept relates to methods of manufacturing semiconductor modules, and more particularly, to a method of manufacturing a semiconductor module using a wafer level package.
"Semiconductor modules may be manufactured through a fabrication process (FAB) for forming semiconductor chips on a substrate, an electrical die sorting (EDS) process for testing electrical characteristics of the semiconductor chips, a process of cutting the substrate to divide and assemble the semiconductor chips, a process of testing electrical characteristics of separated semiconductor chips and a process of mounting the separated semiconductor chips on a module substrate. Since semiconductor modules are manufactured through various processes, manufacturing time increases and production costs increase due to higher facility and material investments."
In addition to obtaining background information on this patent, VerticalNews editors also obtained the inventors' summary information for this patent: "A method of manufacturing a semiconductor module, in accordance with an embodiment of the inventive concept, includes forming semiconductor chips on a bare substrate, performing a burn-in process on the bare substrate including the semiconductor chips, sorting semiconductor chips that exceed a predetermined level of operability determined by testing electrical signal transmission in the semiconductor chips on the burned-in bare substrate, separating the semiconductor chips from one another by cutting the bare substrate, and directly mounting the semiconductor chips on a module substrate A method of manufacturing a semiconductor device, in accordance with an embodiment of the inventive concept, includes forming semiconductor chips on a first substrate, performing a burn-in process on the first substrate including the semiconductor chips, sorting operational semiconductor chips from failed semiconductor chips after the burn-in process, separating the sorted semiconductor chips from one another by cutting the first substrate, and mounting the semiconductor chips on a second substrate.
"The semiconductor chips may be mounted on respective opposite sides of the second substrate.
"The method may further comprise forming a protection pattern to cover the semiconductor chips on the second substrate. The protective pattern may include one of an epoxy molding compound or an aluminum alloy.
"The second substrate may include a plurality of tabs formed below the semiconductor chips, wherein the tabs transmit and receive electric signals to and from the semiconductor chips.
"The semiconductor chips may be spaced apart from each other along a first direction, and include a plurality of conductive patterns positioned between adjacent semiconductor chips.
"The method may further comprise forming a plurality of conductive bumps between each semiconductor chip and the second substrate, wherein the semiconductor chips are spaced apart from each other along a first direction on the second substrate, and the plurality of conductive bumps are formed on a side of each semiconductor chip in a row extending in a second direction perpendicular to the first direction.
"The protection pattern may fill in portions between adjacent conductive bumps."
For more information, see this patent: Kim, Sangyoung; Jung, Jaereyun; Lee, Sanggug; Park, Jongtae. Method of Manufacturing Semiconductor Module. U.S. Patent Number 8741665, filed
Keywords for this news article include: Semiconductor,
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