News Column

Patent Issued for Method of Forming Semiconductor Device

June 18, 2014



By a News Reporter-Staff News Editor at Electronics Newsweekly -- A patent by the inventors Park, Yoonmoon (Seoul, KR); Sim, Jae-Hwang (Seoul, KR); Park, Se-Young (Hwaseong-si, KR); Kim, Keonsoo (Hwaseong-si, KR); Lee, Jaehan (Seoul, KR); Seong, Seungwon (Suwon-si, KR), filed on November 27, 2013, was published online on June 3, 2014, according to news reporting originating from Alexandria, Virginia, by VerticalNews correspondents.

Patent number 8741767 is assigned to Samsung Electronics Co., Ltd. (Suwon-si, Gyeonggi-do, KR).

The following quote was obtained by the news editors from the background information supplied by the inventors: "The present disclosure herein relates to a semiconductor device and a method of forming the same, and more particularly, to a semiconductor device including a cell region and a core region and a method of forming the same.

"Due to multi-functioning and compactness of electronic equipment, semiconductor devices embedded in the electronic equipment are required to be highly integrated and miniaturized. In order to satisfy these requirements of high integration and miniaturization, components of the semiconductor devices should be reduced in size and be disposed at desired positions. However, it may not be easy to form the components with the reduced size and at the desired positions due to restrictions on facilities and processes."

In addition to the background information obtained for this patent, VerticalNews journalists also obtained the inventors' summary information for this patent: "Embodiments are therefore directed to a semiconductor device and a method of forming the same, which substantially overcome one or more of the problems due to the limitations and disadvantages of the related art.

"It is therefore a feature of an embodiment to provide a semiconductor device optimized for high integration and a method of forming the same.

"It is therefore another feature of an embodiment to provide a semiconductor device having improved reliability and a method of forming the same.

"At least one of the above and other features and advantages may be realized by providing a semiconductor device, including a semiconductor substrate having a cell region and a core region adjacent to the cell region, active regions in the cell region and the core region, an interlayer insulating layer covering the active regions, upper cell contacts penetrating the interlayer insulating layer in the cell region, the upper cell contacts being adjacent to each other along a first direction and being electrically connected to the active regions, and core contacts penetrating the interlayer insulating layer in the active regions of the core region, the core contacts being adjacent to each other along the first direction and including upper connection core contacts electrically connected to the active regions, and dummy contacts adjacent to the upper connection core contacts, the dummy contacts being insulated from the active regions.

"In some embodiments, the semiconductor device may further include at least one interconnection extending in a second direction substantially perpendicular to the first direction, the interconnection connecting the upper cell contacts to the core contacts.

"In other embodiments, the interlayer insulating layer may include a first interlayer insulating layer and a second interlayer insulating layer that are sequentially stacked on the semiconductor substrate. The upper cell contacts and the core contacts may penetrate the second interlayer insulating layer.

"In still other embodiments, the semiconductor device may further include lower cell contacts and a lower connection core contacts that penetrate the first interlayer insulating layer. The upper cell contacts may electrically be connected to the active regions of the cell region through the lower cell contacts, and the upper connection core contact may electrically be connected to the active regions of the core region through the lower connection core contact. The dummy contact may be insulated from the active regions by the first interlayer insulating layer.

"In even other embodiments, each upper surface of the upper cell contacts and the core contacts may be coplanar with an upper surface of the second interlayer insulating layer, and each upper surface of the lower cell contacts may be coplanar with an upper surface of the first interlayer insulating layer.

"In yet other embodiments, the semiconductor device may further include contact pads between the first interlayer insulating layer and each of the upper cell contacts and the upper connection core contacts, each contact pad having a larger width than a width of a corresponding upper surface of a lower cell contact or a lower connection core contact.

"In further embodiments, each upper connection core contact may be between two dummy contacts along the first direction.

"In still further embodiments, the cell contacts may be arranged at a first pitch in the first direction and the core contacts may be arranged at a second pitch in the first direction. The second pitch may be equal to or larger than the first pitch.

"In even further embodiments, the active regions may extend in a second direction substantially perpendicular to the first direction, the active regions being adjacent to each other along the first direction, and a plurality of upper connection core contacts may be positioned to contact the adjacent active regions, the upper connection core contacts being adjacent to each other along a third direction nonparallel to the first or second directions.

"In yet further embodiments, a cross-section of the upper cell contacts and the core contacts may have a circular or an oval shape, the cross-section being along a plane parallel to a surface supporting the semiconductor substrate.

"In yet further embodiments, the upper cell contacts may have a substantially same width in the first direction as the core contacts.

"At least one of the above and other features and advantages may also be realized by providing a method of forming a semiconductor device, including defining active regions in a semiconductor substrate including a cell region and a core region adjacent to the cell region, the active regions traversing the cell region and the core region; forming a first interlayer insulating layer on the active regions; forming lower cell contacts that come in contact with the active regions of the cell region and are arranged in a first direction so as to penetrate the first interlayer insulating layer and lower connection core contacts that come in contact with the active regions of the core region and are arranged in the first direction so as to penetrate the first interlayer insulating layer; forming a second interlayer insulating layer on the first interlayer insulating layer; and forming upper cell contacts that are arranged in the first direction so as to be electrically connected to the active regions through the lower cell contacts and upper core contacts that are arranged in the first direction. The upper core contacts and the upper core contacts may be disposed in the second interlayer insulating layer. The upper core contacts may include an upper connection core contact that is electrically connected to the lower connection core contacts and dummy contacts that are insulated from the active regions by the first interlayer insulating layer.

"In some embodiments, the lower cell contacts and the upper cell contacts may be arranged at a first pitch and the core contacts may be arranged at a second pitch. The second pitch may be equal to or larger than the first pitch.

"In other embodiments, the forming of the upper cell contacts and the upper core contacts may include forming a photoresist and a mask on the second interlayer insulating layer. The mask may include patterns for forming the upper cell contacts and the upper core contacts. The patterns for forming the upper cell contacts may substantially have the same pitch in the first direction as the patterns for forming the upper core contacts.

"In still other embodiments, the forming of the upper cell contacts and the upper core contacts may include forming contact holes that penetrate the second interlayer insulating layer and filling a conductive material in the contact holes. The contact holes of the cell region expose the lower cell contact and the first interlayer insulating layer of the core region.

"In even other embodiments, the method may further include forming interconnections, which extend in a second direction intersecting the first direction, on the upper cell contacts and the upper core contacts. The active regions may extend in the second direction, and the interconnections may electrically connect the upper cell contacts and the upper core contacts on one active region.

"In yet other embodiments, the method may further include forming cell contact pads on the lower cell contact and core contact pads on the core region. The forming of the upper cell contacts and the upper core contacts may include forming contact holes that penetrate the second interlayer insulating layer. The contact holes of the cell region may expose the cell pads and the contact holes of the core region may expose the first interlayer insulating layer.

"In further embodiments, the upper cell contacts and the upper core contacts may be formed at the same time to have the same width along the first direction.

"In still further embodiments, the method may further include forming other upper core contacts arranged in parallel with the upper core contacts arranged in the first direction. The upper connection core contacts of the upper core contacts are arranged on the first interlayer insulating layer in a direction non-vertical and nonparallel to the first direction."

URL and more information on this patent, see: Park, Yoonmoon; Sim, Jae-Hwang; Park, Se-Young; Kim, Keonsoo; Lee, Jaehan; Seong, Seungwon. Method of Forming Semiconductor Device. U.S. Patent Number 8741767, filed November 27, 2013, and published online on June 3, 2014. Patent URL: http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=8741767.PN.&OS=PN/8741767RS=PN/8741767

Keywords for this news article include: Semiconductor, Samsung Electronics Co. Ltd..

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Source: Electronics Newsweekly


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