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Patent Issued for Method of Controlling Read Address, Physical Information Acquisition Apparatus, and Semiconductor Device

June 18, 2014



By a News Reporter-Staff News Editor at Electronics Newsweekly -- According to news reporting originating from Alexandria, Virginia, by VerticalNews journalists, a patent by the inventors Okano, Masafumi (Kanagawa, JP); Ui, Hiroki (Tokyo, JP), filed on August 30, 2005, was published online on June 3, 2014.

The assignee for this patent, patent number 8743253, is Sony Corporation (Tokyo, JP).

Reporters obtained the following quote from the background information supplied by the inventors: "In various applications, to detect a physical quantity distribution, a semiconductor device is widely used which includes a linear array or a matrix array of unit elements (pixels) sensitive to a change in a physical quantity such as a pressure or an electromagnetic wave such as light or radiation incident from the outside.

"For example, as shown in FIG. 2B, in video devices, a solid-state image sensor is used which includes an image sensor device (image sensing device) of a CCD (Charge Coupled Device) type, a MOS (Metal Oxide Semiconductor) type, or a CMOS (Complementary Metal-Oxide Semiconductor) type to detect a change in a physical quantity such as light (which is an example of an electromagnetic wave).

"In computer devices, a fingerprint recognition device is used to acquire fingerprint information by detecting an image of a fingerprint based on a change in an electrical or optical characteristic associated with a pressure. In these apparatus, a physical quantity distribution is converted into an electrical signal by unit elements (pixels in the case of a solid-state image sensor) and the resultant electrical signal is read out.

"In some solid-state image sensors, an active pixel sensor (APS) is used in which a driving transistor for amplification is disposed in each image signal generation part that generates an image signal corresponding to a signal charge generated in a charge generation part. This structure is used in many CMOS solid-state image sensors.

"In such an active solid-state image sensing apparatus, to read an image signal, unit pixels arranged in a pixel array part are sequentially selected by controlling addressing, and signals are read from the respective unit pixels. That is, the active solid-state image sensing apparatus is a solid-state image sensor of the address control type.

"For example, in an active pixel sensor of the X-Y addressing type in which unit pixels are arranged in the form of a matrix array, each pixel is configured to have an amplification capability using an active element having a MOS structure (MOS transistor). In this structure, a signal charge (photoelectrons) accumulated in a photodiode serving as a photoelectric conversion device is amplified by the active element and read out as image information.

"In the X-Y addressing solid-state image sensing device of this type, for example, a pixel array part is formed using a large number of pixel transistors arranged in the form of a two-dimensional matrix array. Accumulation of signal charges corresponding to incident light is started on a line-by-line (row-by-row) basis or a pixel-by-pixel basis, and a current or a voltage corresponding to the signal charge accumulated in each pixel is read sequentially from the respective pixels by accessing the pixels by means of addressing.

"In solid-state image sensing devices of the MOS type (and of the CMOS type), the addressing is performed, for example, such that pixels are simultaneously accessed on a line-by-line basis and pixel signals are read from the accessed pixels, that is, pixel signals are read on a line-by-line basis from a pixel array part. In some solid-state image sensing devices of this type, to adapt to the reading scheme of accessing the pixel array part on a line-by-line basis and reading pixels signals from the accessed line, analog-to-digital converters and/or other signal processing units are disposed for respective vertical columns. This configuration is called a column parallel arrangement. Of solid-state image sensing devices with a column-parallel arrangement, a solid-state image sensing device in which a CDS processor or a digital converter is disposed in each vertical column such that pixel signals are sequentially read and output is called a column-type solid-state image sensing device.

"As a result of reductions in size and cost of solid-state image sensing devices such as CCD or CMOS image sensors, various kinds of video devices using a solid-state image sensing device, such as a digital still camera for taking a still image, a portable telephone with a camera, and a video camera for taking a motion image, have come to be widely used. CMOS image sensors can operate with less consumption power and can be produced at a lower cost than CCD image sensors, and thus CMOS image sensors are expected to be widely used instead of CCD image sensors.

"For example, in CMOS image sensors, electrons generated as a result of a photoelectric conversion are accumulated in each pixel, and pixel signals are sequentially read from pixels in pixel columns (vertical columns) specified by address control signals output from a sensor control unit (SCU).

"More specifically, an address setting circuit is disposed in a vertical scanning circuit located close to the pixel array part, and an address control signal is supplied from the address setting circuit to sequentially select pixels. In accordance with the address control signal, the vertical scanning circuit supplies various kinds of control signals (generically referred to as control signals) to the respective pixels via driving buffers thereby turning on/off the pixel transistor at the specified horizontal address position. Thus, the address decoder generates data indicating the address of a pixel to be selected.

"The solid-state image sensing device of the X-Y addressing type is capable of reading a signal from an arbitrary pixel at a specified address, that is, the solid-state image sensing device of this type has a random access capability. Unlike the CCD (Charge Coupled Device) image sensor that reads signal charges from pixels while sequentially selecting pixels using a shift register, the solid-state image sensing device of the X-Y addressing type is capable of arbitrarily setting the order in which to read signals from pixels.

"When pixel signals are read from all pixels, the address setting circuit may be formed using counter circuits (hereinafter, also referred to as address counters). In this case, a vertical address counter and a horizontal address counter are sequentially incremented by '1' to scan all pixels. However, in some cases, it is not necessary to output pixel signals from all pixels.

"For example, in the technique of taking a still image using a digital still camera or the like, it is known to use a CMOS-type solid-state image sensing device with a great number of pixels to obtain a high-resolution still image. In an 'all-pixel read mode', which is a mode to obtain a high-resolution still image, pixel information is read independently from all pixels. However, when there are a great number of pixels, if pixel information is read from all pixels, it is difficult to achieve a sufficiently high frame rate in displaying a motion image on a monitor screen.

"To avoid the above problem, it is known to provide other modes in addition to the 'all-pixel read mode'. More specifically, in a 'decimation read mode', pixel information is read while skipping a particular number of rows or columns. In an 'addition read mode', a particular number of rows or columns (pixels are not necessarily adjacent) are selected, and the sum of pixel information is output. In these modes, as a result of decimation or addition, the number of output pixels is reduced, and thus it is possible to increase the frame rate.

"The decimation read mode is used to display an image with low resolution (corresponding to the number of a liquid crystal monitor) of a subject on the liquid crystal monitor to check the image of the subject. The decimation read mode is also used when a data size of a motion image is reduced by decimating pixel information, and the resultant motion image data is transmitted. The addition read mode is used not only to increase the frame rate by reducing the number of pixels of an output image but also to expand the dynamic range by adding pixel signals of a plurality of rows (for example, two rows).

"In CCD-type image sensors, it is also possible to provide the decimation read mode or the addition read mode. However, because of its structure, the CCD-type image sensor can only read signal charges from pixels while sequentially selecting pixels using a shift register. Therefore, pixel information is first read from all pixels, and then the pixel information is decimated or added by an external signal processing circuit. In contrast, in X-Y addressing image sensors, decimation and addition of image information can be performed on an image sensing part, and an external signal processing circuit for this purpose is not necessary.

"To freely select an order in which to read pixel information from pixels, a particular control mechanism to specify addresses is necessary depending on each mode.

"For example, to decimate image information by a factor of 2 in both vertical and horizontal directions, the address counter is increased in steps of 2. That is, it is needed to change the steps in which to increase the address counter, depending on the mode.

"Typically, address values are represented using a binary code or a Gray code.

"When address values are represented in binary code, it is possible to easily realize a circuit for adding an address value with an arbitrary value, and thus it is possible to easily change the steps in which to increase the address value.

"However, it is known that noise is generated when the data value inverts, and the noise can propagate via a power supply line or space. That is, the address counter can be a source of noise, whose state randomly changes because the number of inverting bits in data (hereinafter referred to as the number of toggled bits) changes randomly. If noise is generated in a constant state, it may be possible to deal with the generated noise. However, when the number of toggled bits randomly changes, it is difficult to deal with noise.

"When the value changed from '0' to '1', only one bit is toggled. This is the smallest case in terms of the number of toggled bits. On the other hand, when a carry occurs from a lowest-order bit to a highest-order bit, all bits are toggled. This is the greatest case in terms of the number of toggled bits.

"Because power source noise of the address counter varies depending on the randomly varying number of toggled bits as described above, the power source noise has a bad influence on an image.

"FIGS. 23 and 24 show examples of relationships among accessed pixels, the address value, and the number of toggled bits for a case in which the binary code or the Gary code is used. More specifically, FIG. 23 shows an example of a manner in which the address value is increased in steps of 3, and FIG. 24 shows an example of a manner in which the address value is increased in steps of 5.

"In both examples shown in FIGS. 23 and 24, the number of toggled bits of the binary code changes in a great range of 2 to 4.

"One technique of reducing the number of toggled bits is to use Gray code. In the Gray code, when the address value is increased in steps of 1, a change occurs only in one bit. That is, the Gray code provides the least number of toggled bits and thus provides least noise.

"However, even when the Gray code is used to express the address value, if the address value is increased in steps other than '1' as in the examples shown in FIGS. 23 and 24, the number of toggled bits also varies in a range of 1 to 3.

"Another problem with the Gray code is that, unlike the binary code, it is difficult to realize a simple circuit capable of increasing the address value in various specified steps, but a complicated circuit is needed. The complexity of the circuit causes an increase in noise.

"As described above, in the technique of increasing the address value using the counter based on the binary code or the Gray code, it is difficult to perform addressing in various modes needed, for example, in decimation while maintaining the change in the number of toggled bits within a small range which would make it easy to handle a problem associated with noise arising from the change in the number of toggled bits.

"The above-described problem can occur not only in systems using an image sensing device but also in semiconductor systems using a semiconductor device such as a semiconductor memory in which the manner of addressing in the reading operation is allowed to be changed to a certain extent.

"In view of the above, it is an object of the present invention to provide a technique of switching the manner of addressing as required depending on the reading mode, while maintaining the change in the number of toggled bits within a small range without needing a complicated circuit for addressing."

In addition to obtaining background information on this patent, VerticalNews editors also obtained the inventors' summary information for this patent: "The present invention provides a method of controlling a read address, in a semiconductor device including a plurality of unit elements arranged in the form of a one-dimensional or two-dimensional array, so as to specify an address value of a unit element from which to read a signal, wherein the address value is divided into a high-order address value and a low-order address value, and the high-order address value and the low-order address value are set by address setting units that operate differently from each other.

"The present invention provides a physical information acquisition apparatus and a semiconductor device advantageously using the method of controlling a read address, wherein the physical information acquisition apparatus or the semiconductor device includes a low-order address value setting unit for setting a low-order address value of an address value indicating a location of one of unit elements from which to read a signal, and a high-order address value setting unit for setting a high-order address value of the address value indicating the location of the one of unit elements from which to read the signal, wherein the high-order address value setting unit sets the high-order address value in a manner different from the manner in which the low-order address value setting unit sets the low-order address value."

For more information, see this patent: Okano, Masafumi; Ui, Hiroki. Method of Controlling Read Address, Physical Information Acquisition Apparatus, and Semiconductor Device. U.S. Patent Number 8743253, filed August 30, 2005, and published online on June 3, 2014. Patent URL: http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=8743253.PN.&OS=PN/8743253RS=PN/8743253

Keywords for this news article include: Electronics, Electromagnet, Semiconductor, Sony Corporation, Signal Processing.

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Source: Electronics Newsweekly


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