News Column

Patent Issued for Method for Making Photomask Layout

June 18, 2014



By a News Reporter-Staff News Editor at Electronics Newsweekly -- United Microelectronics Corp. (Hsinchu, TW) has been issued patent number 8745547, according to news reporting originating out of Alexandria, Virginia, by VerticalNews editors.

The patent's inventors are Kuo, Shih-Ming (Tainan, TW); Chen, Ming-Jui (Hsinchu, TW); Hsieh, Te-Hsien (Kaohsiung, TW); Wang, Cheng-Te (Hsinchu, TW); Lee, Jing-Yi (Tainan, TW).

This patent was filed on July 11, 2013 and was published online on June 3, 2014.

From the background information supplied by the inventors, news correspondents obtained the following quote: "The present invention relates to the design and manufacture of an integrated circuit (IC), and particularly to a method for making a photomask layout.

"As the level of integration of integrated circuits is increased, the demand for increasing the feature density or reducing the pitch size becomes the mainstream in the semiconductor industry, and the key technology is in photolithography. In the photolithographic module, the accuracy in the pattern transferring process from a photomask to a wafer is quite important.

"When the line-width drops to one half or less of the wavelength of the light source for exposure, several correction and verification steps are required to perform to the whole graphic data of a photomask, so as to reduce the deviation of the critical dimension on the wafer during the pattern transferring process. However, the graphic data system (GDS) file of the photomask used in advanced IC processes easily has a size up to hundreds of gigabytes, so it is very time-consuming to perform the said correction and verification steps."

Supplementing the background information on this patent, VerticalNews reporters also obtained the inventors' summary information for this patent: "Accordingly, the present invention provides a method for making a photomask layout, with which the CPU run time can be greatly reduced.

"The present invention provides a method for making a photomask layout. A graphic data of a photomask is provided. A first correction step is performed to the graphic data. A first verification step is performed to all of the graphic data which has been subjected to the first correction step, wherein at least one failed pattern not passing the first verification step is found. A second correction step is performed to the at least one failed pattern, so as to obtain at least one modified pattern. A second verification step is performed only to at least one buffer region covering the at least one modified pattern, wherein the buffer region has an area less than a whole area of the photomask. Besides, each of the first correction step, the first verification step, the second correction step and the second verification step is executed by a computer.

"According to an embodiment of the present invention, the buffer region further covers a region optically affected by the at least one modified pattern.

"According to an embodiment of the present invention, each of the at least one buffer region is set to have the same shape and size.

"According to an embodiment of the present invention, each of the at least one buffer region is set to have a different shape and size.

"According to an embodiment of the present invention, the at least one buffer region is set to have an area about 500% larger than an area of the at least one modified pattern.

"According to an embodiment of the present invention, the at least one buffer region is determined by an optical model.

"According to an embodiment of the present invention, the first verification step includes a design rule check, a lithography rule check or a combination thereof.

"According to an embodiment of the present invention, the second verification step includes a design rule check, a lithography rule check or a combination thereof.

"According to an embodiment of the present invention, the first verification step and the second verification step include the same type of rule check.

"According to an embodiment of the present invention, the first correction step includes an optical proximity correction (OPC).

"According to an embodiment of the present invention, the second correction step includes an OPC.

"According to an embodiment of the present invention, the first correction step is executed by a first electronic design automation (EDA) tool, the second correction step is executed by a second EDA tool different from the first EDA tool.

"According to an embodiment of the present invention, the first correction step, the first verification step, the second correction step and the second verification step form a close loop.

"In view of the above, during the photomask layout process, once patterns fail to pass the process rule check and are therefore modified, a verification step of the invention is performed only to the modified patterns but not to the whole graphic data including modified and unmodified patterns. As a result, the CPU run time can be greatly reduced, thereby achieving competitive advantages over competitors.

"In order to make the aforementioned and other objects, features and advantages of the present invention comprehensible, a preferred embodiment accompanied with figures is described in detail below."

For the URL and additional information on this patent, see: Kuo, Shih-Ming; Chen, Ming-Jui; Hsieh, Te-Hsien; Wang, Cheng-Te; Lee, Jing-Yi. Method for Making Photomask Layout. U.S. Patent Number 8745547, filed July 11, 2013, and published online on June 3, 2014. Patent URL: http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=8745547.PN.&OS=PN/8745547RS=PN/8745547

Keywords for this news article include: United Microelectronics Corp.

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Source: Electronics Newsweekly


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