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Patent Issued for Metal Oxide Semiconductor (MOS) Device with Locally Thickened Gate Oxide

June 18, 2014



By a News Reporter-Staff News Editor at Electronics Newsweekly -- From Alexandria, Virginia, VerticalNews journalists report that a patent by the inventors Dornel, Erwan (Fontaine, FR); Tannhof, Pascal R. (Fontainebleau, FR); Rideau, Denis (Grenoble, FR), filed on May 18, 2012, was published online on June 3, 2014.

The patent's assignee for patent number 8741704 is International Business Machines Corporation (Armonk, NY).

News editors obtained the following quote from the background information supplied by the inventors: "The present disclosure relates generally to semiconductor devices. More particularly, the present disclosure relates to scaling of semiconductor devices.

"In order to be able to make integrated circuits (ICs), such as memory, logic, and other devices, of higher integration density than currently feasible, one has to find ways to further downscale the dimensions of field effect transistors (FETs), such as metal-oxide-semiconductor field effect transistors (MOSFETs) and complementary metal oxide semiconductors (CMOS). Scaling achieves compactness and improves operating performance in devices by shrinking the overall dimensions and operating voltages of the device while maintaining the device's electrical properties."

As a supplement to the background information on this patent, VerticalNews correspondents also obtained the inventors' summary information for this patent: "A method of fabricating a semiconductor device is provided that, in one embodiment, includes providing a gate structure on a channel portion of a semiconductor substrate, wherein the gate structure includes at least one gate dielectric on the channel portion of the semiconductor substrate and at least one gate conductor on the at least one gate dielectric. An edge portion of the at least one gate dielectric is removed from each side of the gate structure. Removing the edge portion of the gate dielectric provides an exposed base edge of the at least one gate conductor and an exposed channel surface of the semiconductor substrate underlying the gate structure. The sidewall of the gate structure is oxidized. The oxidizing of the sidewall of the gate structure also oxidizes at least one of the exposed base edges of the at least one gate conductor and the exposed channel surface of the semiconductor substrate that is underlying the gate structure.

"In another aspect, a semiconductor device is provided that includes a gate structure on a semiconductor substrate, in which the gate structure includes at least one gate conductor and at least one gate dielectric. The at least one gate dielectric includes a dielectric layer that is in direct contact with a surface of the semiconductor substrate, in which edge portions of the dielectric layer have a greater thickness than a central portion of the dielectric layer. The lower surface of the edge portion of the dielectric layer extends into the semiconductor substrate. The gate conductor is present on an upper surface of the edge portions.

"In another aspect, a method of fabricating a semiconductor device is provided that in one embodiment includes providing a gate structure on a channel portion of a semiconductor substrate, wherein the gate structure includes at least one gate dielectric on the channel portion of the semiconductor substrate and at least one gate conductor on the at least one gate dielectric. An edge portion of the at least one gate dielectric is removed on each side of the gate structure, wherein the removing of the edge portion of the at least one gate dielectric provides an exposed base edge of the at least one gate conductor and an exposed channel surface of the semiconductor substrate underlying the gate structure. A sidewall of the gate structure is nitrided, wherein the nitriding of the sidewall of the gate structure also nitrides at least one of the exposed base edge of the at least one gate conductor and the exposed channel surface of the semiconductor substrate that is underlying the gate structure."

For additional information on this patent, see: Dornel, Erwan; Tannhof, Pascal R.; Rideau, Denis. Metal Oxide Semiconductor (MOS) Device with Locally Thickened Gate Oxide. U.S. Patent Number 8741704, filed May 18, 2012, and published online on June 3, 2014. Patent URL: http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=8741704.PN.&OS=PN/8741704RS=PN/8741704

Keywords for this news article include: Electronics, Semiconductor, International Business Machines Corporation.

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Source: Electronics Newsweekly


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