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Patent Application Titled "Isolating Failing Latches Using a Logic Built-In Self-Test" Published Online

June 17, 2014



By a News Reporter-Staff News Editor at Information Technology Newsweekly -- According to news reporting originating from Washington, D.C., by VerticalNews journalists, a patent application by the inventors Al-omari, Ra'ed M. (Round Rock, TX); Harper, Micheal W. (Round Rock, TX); Phan, Cindy (Pflugerville, TX); Riley, Mack W. (Austin, TX), filed on November 29, 2012, was made available online on June 5, 2014.

The assignee for this patent application is International Business Machines Corporation.

Reporters obtained the following quote from the background information supplied by the inventors: "The present application relates generally to an improved data processing apparatus and method and more specifically to mechanisms for testing integrated circuits and more specifically to isolating failing latches within an integrated circuit using a logic built-in self-test (LBIST).

"Testing of integrated circuit devices is an important factor in ensuring proper functionality of the integrated circuit devices as well as for determining the functional capabilities of the integrated circuit devices for categorization purposes. As integrated circuit devices have become more complex, in an effort to reduce the complexity and cost of the external testing equipment, testing of the integrated circuit devices has moved from the exclusive use of external testing equipment to greater dependence on built-in self-test (BIST) circuitry provided on the integrated circuit device itself. Such BIST circuitry may be used to test the functional logic of the integrated circuit device (LBIST), arrays of the integrated circuit device (ABIST), or the like.

"Typically, with LBIST circuitry provided on the integrated circuit device, a test pattern generator generates a test pattern that is applied to the functional logic of the integrated circuit device, or circuit under test (CUT), which in turn outputs a response to a response analyzer that generates a signature based on the analyzed response. With LBIST, all of the logic on the integrated circuit device is tested using a large number of test patterns to ensure high test coverage. The resultant data generated by the logic of the integrated circuit device is captured in 'strings' of output latches of the integrated circuit device. After all of the scheduled tests have been completed, the final result is compared to a final result generated by a simulation or an integrated circuit device that is known to operate properly. Based upon this comparison, the integrated circuit device under test may be identified as working properly or incorrectly. However, current LBIST circuitry only identifies whether the entire integrated circuit device under test is defective or not."

In addition to obtaining background information on this patent application, VerticalNews editors also obtained the inventors' summary information for this patent application: "In one illustrative embodiment, a method, in an integrated circuit device, is provided for identifying a failing latch within the integrated circuit device. The illustrative embodiment loads a set of expected values for a set of scan chains associated with an identified failing multiple input signature register into a data structure. The illustrative embodiment initializes a counter to an initial value. The illustrative embodiment initiates a test sequence on the set of scan chains associated with the identified failing multiple input signature register. In the illustrative embodiment, the test sequence comprises a set of test portions. For each of the set of test portions, the illustrative embodiment compares an output of the multiple input signature register to a corresponding value in the set of expected values. Responsive to determining a match between the output of the multiple input signature register to the corresponding value in the set of expected values, the illustrative embodiment increments the counter. Responsive to determining that the output of the multiple input signature register does not match the corresponding value in the set of expected values, the illustrative embodiment stops the increment of the latch counter and reads out the value of the counter to identify the failing latch in the integrated circuit device.

"In other illustrative embodiments, an integrated circuit device comprising a logic built-in self-test device for identifying a failing latch within the integrated circuit device is provided. The logic built-in self-test device performs various ones of, and combinations of, the operations outlined above with regard to the method illustrative embodiment.

"In yet another illustrative embodiment, a data processing system comprising an integrated circuit device that further comprises a logic built-in self-test device for identifying a failing latch within the integrated circuit device is provided. The logic built-in self-test device performs various ones of, and combinations of, the operations outlined above with regard to the method illustrative embodiment.

"These and other features and advantages of the present invention will be described in, or will become apparent to those of ordinary skill in the art in view of, the following detailed description of the example embodiments of the present invention.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS

"The invention, as well as a preferred mode of use and further objectives and advantages thereof, will best be understood by reference to the following detailed description of illustrative embodiments when read in conjunction with the accompanying drawings, wherein:

"FIG. 1 is an example block diagram of a computing device in which aspects of the illustrative embodiments may be implemented:

"FIG. 2A is an exemplary block diagram of the primary operational components used for LBIST testing in accordance with an illustrative embodiment;

"FIG. 2B is an exemplary block diagram of LBIST logic of an integrated circuit device for performing LBIST testing in accordance with an illustrative embodiment;

"FIG. 3 depicts an exemplary block diagram of enhanced LBIST logic configuration of an integrated circuit device in accordance with an illustrative embodiment; and

"FIG. 4 shows a block diagram of an exemplary design flow used, for example, in semiconductor IC logic design, simulation, test, layout, and manufacture."

For more information, see this patent application: Al-omari, Ra'ed M.; Harper, Micheal W.; Phan, Cindy; Riley, Mack W. Isolating Failing Latches Using a Logic Built-In Self-Test. Filed November 29, 2012 and posted June 5, 2014. Patent URL: http://appft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&u=%2Fnetahtml%2FPTO%2Fsearch-adv.html&r=340&p=7&f=G&l=50&d=PG01&S1=20140529.PD.&OS=PD/20140529&RS=PD/20140529

Keywords for this news article include: Information Technology, Information and Data Processing, International Business Machines Corporation.

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Source: Information Technology Newsweekly


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