The assignee for this patent application is
Reporters obtained the following quote from the background information supplied by the inventors: "The present invention relates to data processing, and more specifically, to a coherent proxy for an attached processor.
"A conventional distributed shared memory computer system, such as a server computer system, includes multiple processing units all coupled to a system interconnect, which typically comprises one or more address, data and control buses. Coupled to the system interconnect is a system memory, which represents the lowest level of volatile memory in the multiprocessor computer system and generally is accessible for read and write access by all processing units. In order to reduce access latency to instructions and data residing in the system memory, each processing unit is typically further supported by a respective multi-level cache hierarchy, the lower level(s) of which may be shared by one or more processor cores.
"Because multiple processor cores may request write access to a same memory block (e.g., cache line or sector) and because cached memory blocks that are modified are not immediately synchronized with system memory, the cache hierarchies of multiprocessor computer systems typically implement a cache coherency protocol to ensure at least a minimum required level of coherence among the various processor core's 'views' of the contents of system memory. The minimum required level of coherence is determined by the selected memory consistency model, which defines rules for the apparent ordering and visibility of updates to the distributed shared memory. In all memory consistency models in the continuum between weak consistency models and strong consistency models, cache coherency requires, at a minimum, that after a processing unit accesses a copy of a memory block and subsequently accesses an updated copy of the memory block, the processing unit cannot again access the old ('stale') copy of the memory block.
"A cache coherency protocol typically defines a set of cache states stored in association with cached copies of memory blocks, as well as the events triggering transitions between the cache states and the cache states to which transitions are made. Coherency protocols can generally be classified as directory-based or snoop-based protocols. In directory-based protocols, a common central directory maintains coherence by controlling accesses to memory blocks by the caches and by updating or invalidating copies of the memory blocks held in the various caches. Snoop-based protocols, on the other hand, implement a distributed design paradigm in which each cache maintains a private directory of its contents, monitors ('snoops') the system interconnect for memory access requests targeting memory blocks held in the cache, and responds to the memory access requests by updating its private directory, and if required, by transmitting coherency message(s) and/or its copy of the memory block.
"The cache states of the coherency protocol can include, for example, those of the well-known MESI (Modified, Exclusive, Shared, Invalid) protocol or a variant thereof. The MESI protocol allows a cache line of data to be tagged with one of four states: 'M' (Modified), 'E' (Exclusive), 'S' (Shared), or 'I' (Invalid). The Modified state indicates that a memory block is valid only in the cache holding the Modified memory block and that the memory block is not consistent with system memory. The Exclusive state indicates that the associated memory block is consistent with system memory and that the associated cache is the only cache in the data processing system that holds the associated memory block. The Shared state indicates that the associated memory block is resident in the associated cache and possibly one or more other caches and that all of the copies of the memory block are consistent with system memory. Finally, the Invalid state indicates that the data and address tag associated with a coherency granule are both invalid."
In addition to obtaining background information on this patent application, VerticalNews editors also obtained the inventors' summary information for this patent application: "In at least one embodiment, a coherent attached processor proxy (CAPP) of a primary coherent system receives a memory access request from an attached processor (AP) and an expected coherence state of a target address of the memory access request with respect to a cache memory of the AP. In response, the CAPP determines a coherence state of the target address and whether or not the expected state matches the determined coherence state. In response to determining that the expected state matches the determined coherence state, the CAPP issues a memory access request corresponding to that received from the AP on a system fabric of the primary coherent system. In response to determining that the expected state does not match the coherence state determined by the CAPP, the CAPP transmits a failure message to the AP without issuing on the system fabric a memory access request corresponding to that received from the AP.
"In at least one embodiment, in response to receiving a memory access request and expected coherence state at an attached processor at a coherent attached processor proxy (CAPP), the CAPP determines that a conflicting request is being serviced. In response to determining that the CAPP is servicing a conflicting request and that the expected state matches, a master machine of the CAPP is allocated in a Parked state to service the memory access request after completion of service of the conflicting request. The Parked state prevents servicing by the CAPP of a further conflicting request snooped on the system fabric. In response to completion of service of the conflicting request, the master machine transitions out of the Parked state and issues on the system fabric a memory access request corresponding to that received from the AP.
"In at least one embodiment, a coherent attached processor proxy (CAPP) within a primary coherent system participates in an operation on a system fabric of the primary coherent system on behalf of an attached processor (AP) that is external to the primary coherent system and that is coupled to the CAPP. The operation includes multiple components communicated with the CAPP including a request and at least one coherence message. The CAPP determines one or more of the components of the operation by reference to at least one programmable data structure within the CAPP that can be reprogrammed.
BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS
"FIG. 1 is a high level block diagram of an exemplary data processing system in which a coherent device participates with a primary coherent system across a communication link through a proxy;
"FIG. 2 is a more detailed block diagram of an exemplary embodiment of the data processing system of FIG. 1;
"FIG. 3 is a more detailed block diagram of an exemplary embodiment of a processing unit in the data processing system of FIG. 2;
"FIG. 4 is a time-space diagram of an exemplary operation on the system fabric of the data processing system of FIG. 2;
"FIG. 5 is a more detailed block diagram of an exemplary embodiment of the coherent attached processor proxy (CAPP) in the processing unit of FIG. 3;
"FIG. 6 is a high level logical flowchart of an exemplary process by which a CAPP coherently handles a memory access request received from an attached processor (AP) in accordance with one embodiment;
"FIG. 7 is a high level logical flowchart of an exemplary process by which a CAPP coherently handles a snooped memory access request in accordance with one embodiment;
"FIG. 8 is a first time-space diagram of an exemplary processing scenario in which an AP requests to coherently update a memory block within the primary coherent system to which it is attached;
"FIG. 9 is a second time-space diagram of an exemplary processing scenario in which an AP requests to coherently update a memory block within the primary coherent system to which it is attached;
"FIG. 10 is a third time-space diagram of an exemplary processing scenario in which an AP requests to coherently update a memory block within the primary coherent system to which it is attached; and
"FIG. 11 is a data flow diagram of an exemplary design process."
For more information, see this patent application: BLANER, BARTHOLOMEW; CUMMINGS, DAVID W.;
Keywords for this news article include: Information Technology, Information and Data Processing,
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