News Column

"Addressing, Command Protocol, and Electrical Interface for Non-Volatile Memories Utilized in Recording Usage Counts" in Patent Application Approval...

June 17, 2014



"Addressing, Command Protocol, and Electrical Interface for Non-Volatile Memories Utilized in Recording Usage Counts" in Patent Application Approval Process

By a News Reporter-Staff News Editor at Information Technology Newsweekly -- A patent application by the inventors Booth, James Ronald (Nicholasville, KY); Willett, Bryan Scott (Lexington, KY), filed on October 14, 2013, was made available online on June 5, 2014, according to news reporting originating from Washington, D.C., by VerticalNews correspondents.

This patent application is assigned to Lexmark International, Inc.

The following quote was obtained by the news editors from the background information supplied by the inventors: "Non-volatile memory modules are commonly found in computing devices for recording the usage of components, including consumable components having a limited life span. For instance, non-volatile memory modules are common in imaging and printing devices, such as in multifunction printers, for recording the use of components such as fusers, accumulation belts, and the like, and for recording the use of consumables such as print cartridges. In imaging or printing devices, for instance, usage may be recorded based upon the number of pages printed by the device, or based upon the partial or full depletion of the print cartridges. Such usage counts are helpful in a variety of ways, including for billing purposes and in monitoring the status and/or use of consumable components.

"As computing devices have advanced and become more complex, the number of non-volatile memory modules included within each device has increased. The speed with which each non-volatile memory module must be updated or read in a computing device has also increased. Continuing with the illustrative example of printing and imaging devices, the speed and page rates of these devices are constantly improving. Therefore, not only do the contents of a greater number of non-volatile memory modules have to be updated, but the contents of these memory modules must be updated in a shorter amount of time to keep up with the faster page rates. In imaging and printing devices, because conventional many memory modules have relatively long wait times for updating, faster page rates present difficulties in updating each of the non-volatile memories in a device in a timely manner.

"In addition, non-volatile memory modules (e.g., EEPROM, NOR flash memory, NAND flash memory, etc.) in computing devices may experience degradation during operation, thereby necessitating error handling to mitigate interruption of operation of the memory modules. Further, non-volatile memory modules may be physically part of removeable and/or consumable components of a computing device, such as printer cartridges. Because such removeable and/or consumable components should be easily installed and removed by users, there is a cost premium associated with each electrical connection between the computing device and it's removeable and/or consumable component, as exists, for instance, with a printing device and a printer cartridge. By utilizing multi-level or analog level communication techniques appropriately, the number of these electrical connections can be minimized, thereby helping to increase reliability and decrease cost.

"Conventional protocols do not sufficiently handle all of these problems discussed. Thus, there remains an unsatisfied need in the industry for addressing schemes, command protocols, and electrical interfaces for quickly updating non-volatile memories, such as in non-volatile memory modules utilized in imaging and printing devices."

In addition to the background information obtained for this patent application, VerticalNews journalists also obtained the inventors' summary information for this patent application: "The present invention overcomes the disadvantages of the prior art by providing addressing schemes, command protocols, and electrical interfaces that quickly update memory modules, such as non-volatile memory modules, in computing devices such as imaging and printing devices.

"According to one embodiment of the present invention, there is a method of updating memory modules. The method includes receiving, at a first memory module, a first command transmitted from a processing device, transmitting, from the first memory module to a processing device, a first indication that the first command was received without error, receiving at a second memory module, a second command transmitted from the processing device, wherein the processing device transmits the second command responsive responsive to receiving the first indication transmitted from the first memory module, and transmitting, from the second memory module to the processing device, a second indication that the command was received without error, where the first and second processing modules process the respective first and second commands, at least in part, concurrently.

"According to an aspect of the invention, the second memory module receiving the second command transmitted from the memory module may occur concurrently, at least in part, with the first memory module processing the first command. In addition, the second memory module transmitting the second indication to the processing device may occur concurrently, at least in part, with the first memory module processing the first command. According to another aspect of the invention, a time associated with the first memory module processing the first command may be greater than a time associated with the first memory module receiving the first command and transmitting the first indication. A time associated with the first memory module processing the first command may be substantially the same as a time associated with the second memory module processing the second command. Likewise, a time associated with the first memory module receiving the first command and transmitting the first indication may be substantially the same as a time associated with the second memory module receiving the second command and transmitting the second indication.

"In accordance with another aspect of the invention, the first command and the second command are substantially the same. The first command and the second command may be associated with updating contents of the respective first and second memory modules. The first and second commands may include an increment counter command operable to instruct the respect first memory module and second memory module to increment a counter. According to another aspect of the invention, the first and second commands may each comprise a command associated with one or more cryptographic operations such as encryption or decryption.

"According to another embodiment of the present invention, there is a method of communicating with memory modules. The method includes determining, at a processing device, that the first and second memory modules are ready to receive data, generating, at the processing device, a first packet comprising a first command and a first memory module address associated with the first memory module, transmitting the first packet from the processing device to the first memory module, receiving, at the processing device, a first confirmation signal from the first memory module, the first confirmation signal indicating that the first memory module received the first command without error, and in response to receiving the first confirmation signal, generating, at the processing device, a second packet comprising a second command and a second memory module address associated with the second memory module. The method further includes transmitting the second packet from the processing device to the second memory module, and receiving, at the processing device, a second confirmation signal from the second memory module, the second confirmation signal indicating that the second memory module received the second command without error, where the first and second memory modules process at least a portion of the respective first and second commands concurrently.

"According to an aspect of the present invention, the second command is substantially the same as the first command. The first and second commands may each comprise one or both of a decryption command and a encryption command. According to another aspect of the invention, at least a portion of a time associated with the processing device transmitting the second packet and receiving the second confirmation signal may occur concurrently with a time associated with the first memory module processing the first command. The time associated with the first memory module processing the first command may be substantially larger than a time associated with the processing device transmitting the second packet and receiving the second confirmation signal.

"According to yet another embodiment of the present invention, there is a method of updating memory modules. The method includes during a first time period, a first memory module receiving a first command from a processing device and transmitting a first signal to the processing device, the first signal indicating a successful reception of the first command, during a second time period immediately following the first time period, the first memory module processing the first command, where the second time period is substantially greater than the first time period, during a third time period immediately following the first time period and overlapping at least in part with a beginning of the second time period, a second memory module receiving a second command from the processing device and transmitting the second signal to the processing device, the second signal indicating a successful reception of the second command, and during a fourth time period immediately following the third time period and overlapping the second time period, the second memory module processing the second command.

"According to an aspect of the present invention, the first and second commands are substantially the same, thereby making the lengths of the second time period and fourth time periods substantially the same. The lengths of the first and third time periods may also be substantially the same. The lengths of the second and fourth time periods may be substantially larger than the lengths of the first and third time periods. According to another aspect of the invention, each of the first and second commands may be associated with write commands and cryptographic commands.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWING(S)

"Having thus described the invention in general terms, reference will now be made to the accompanying drawings, which are not necessarily drawn to scale, and wherein:

"FIG. 1A is a schematic of an illustrative electrical interface, according to an embodiment of the present invention.

"FIG. 1B is a schematic of an alternative manner by which the electrical interface of FIG. 1A may be achieved by an electronic assembly including integrated circuits, according to an illustrative embodiment of the present invention.

"FIG. 1C is a schematic of an illustrative electrical interface, according to an embodiment of the present invention.

"FIGS. 2A and 2B are illustrative memory module addresses according to an embodiment of the present invention.

"FIG. 3 is a block diagram flow chart of a write data operation, according to an illustrative embodiment of the present invention

"FIGS. 4A and 4B are illustrative command protocols, according to an embodiment of the present invention.

"FIG. 5 is a block diagram flow chart of a read data operation, according to an illustrative embodiment of the present invention.

"FIGS. 6A and 6B are illustrative command protocols according, to an embodiment of the present invention.

"FIG. 7 shows a block diagram flow chart illustrating a method of communicating with one or more memory modules, according to one embodiment of the present invention.

"FIG. 8A is a time-flow diagram for a broadcast scheme, according to an embodiment of the present invention.

"FIG. 8B is a time-flow diagram for a split transaction scheme, according to an embodiment of the present invention."

URL and more information on this patent application, see: Booth, James Ronald; Willett, Bryan Scott. Addressing, Command Protocol, and Electrical Interface for Non-Volatile Memories Utilized in Recording Usage Counts. Filed October 14, 2013 and posted June 5, 2014. Patent URL: http://appft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&u=%2Fnetahtml%2FPTO%2Fsearch-adv.html&r=3527&p=71&f=G&l=50&d=PG01&S1=20140529.PD.&OS=PD/20140529&RS=PD/20140529

Keywords for this news article include: Information Technology, Lexmark International Inc, Information and Data Encoding and Encryption.

Our reports deliver fact-based news of research and discoveries from around the world. Copyright 2014, NewsRx LLC


For more stories covering the world of technology, please see HispanicBusiness' Tech Channel



Source: Information Technology Newsweekly


Story Tools






HispanicBusiness.com Facebook Linkedin Twitter RSS Feed Email Alerts & Newsletters